Xing Hu

Orcid: 0000-0002-9979-0561

Affiliations:

University of California, Santa Barbara, Department of Electrical and Computer Engineering, CA, USA
University of Chinese Academy of Sciences, State Key Laboratory of Computer Architecture, Institute of Computing Technology, Beijing, China (former)

According to our database¹, Xing Hu authored at least 80 papers between 2011 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Bibliography

2024

Real-Time Robust Video Object Detection System Against Physical-World Adversarial Attacks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024

2023

Learning controllable elements oriented representations for reinforcement learning.

[BibT_eX]

[DOI]

Neurocomputing, September, 2023

DyPipe: A Holistic Approach to Accelerating Dynamic Neural Networks with Dynamic Pipelining.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., July, 2023

Comprehensive SNN Compression Using ADMM Optimization and Activity Regularization.

[BibT_eX]

[DOI]

IEEE Trans. Neural Networks Learn. Syst., June, 2023

Exploring Adversarial Attack in Spiking Neural Networks With Spike-Compatible Gradient.

[BibT_eX]

[DOI]

IEEE Trans. Neural Networks Learn. Syst., May, 2023

Can Protective Perturbation Safeguard Personal Data from Being Exploited by Stable Diffusion?

[BibT_eX]

[DOI]

Rui Zhangp Zidong Dup Qi Guo

Xing Hu

CoRR, 2023

Context Shift Reduction for Offline Meta-Reinforcement Learning.

[BibT_eX]

[DOI]

CoRR, 2023

Efficient Symbolic Policy Learning with Differentiable Symbolic Expression.

[BibT_eX]

[DOI]

CoRR, 2023

Self-driven Grounding: Large Language Model Agents with Automatical Language-aligned Skill Learning.

[BibT_eX]

[DOI]

CoRR, 2023

Pushing the Limits of Machine Design: Automated CPU Design with AI.

[BibT_eX]

[DOI]

CoRR, 2023

Flew Over Learning Trap: Learn Unlearnable Samples by Progressive Staged Training.

[BibT_eX]

[DOI]

CoRR, 2023

Unlearnable Examples for Diffusion Models: Protect Data from Unauthorized Exploitation.

[BibT_eX]

[DOI]

CoRR, 2023

ANPL: Compiling Natural Programs with Interactive Decomposition.

[BibT_eX]

[DOI]

CoRR, 2023

Ultra-low Precision Multiplication-free Training for Deep Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2023

Online Symbolic Regression with Informative Query.

[BibT_eX]

[DOI]

CoRR, 2023

Contrastive Modules with Temporal Attention for Multi-Task Reinforcement Learning.

[BibT_eX]

[DOI]

Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023

Cambricon-R: A Fully Fused Accelerator for Real-Time Learning of Neural Scene Representation.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

Online Prototype Alignment for Few-shot Policy Transfer.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Machine Learning, 2023

BALTO: fast tensor program optimization with diversity-based active learning.

[BibT_eX]

[DOI]

Proceedings of the Eleventh International Conference on Learning Representations, 2023

Heron: Automatically Constrained High-Performance Library Generation for Deep Learning Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

Conceptual Reinforcement Learning for Language-Conditioned Tasks.

[BibT_eX]

[DOI]

Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023

2022

Cambricon-G: A Polyvalent Energy-Efficient Accelerator for Dynamic Graph Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Rubik: A Hierarchical Architecture for Efficient Graph Neural Network Training.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Enabling One-Size-Fits-All Compilation Optimization for Inference Across Machine Learning Computers.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2022

A Systematic View of Model Leakage Risks in Deep Neural Network Systems.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2022

Real-Time Robust Video Object Detection System Against Physical-World Adversarial Attacks.

[BibT_eX]

[DOI]

CoRR, 2022

Object-Category Aware Reinforcement Learning.

[BibT_eX]

[DOI]

Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022

Causality-driven Hierarchical Structure Discovery for Reinforcement Learning.

[BibT_eX]

[DOI]

Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022

Toward Robust Spiking Neural Network Against Adversarial Perturbation.

[BibT_eX]

[DOI]

Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022

Cambricon-P: A Bitflow Architecture for Arbitrary Precision Computing.

[BibT_eX]

[DOI]

Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

BabelTower: Learning to Auto-parallelized Program Translation.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Machine Learning, 2022

Neural Program Synthesis with Query.

[BibT_eX]

[DOI]

Proceedings of the Tenth International Conference on Learning Representations, 2022

2021

Effective and Efficient Batch Normalization Using a Few Uncorrelated Data for Statistics Estimation.

[BibT_eX]

[DOI]

IEEE Trans. Neural Networks Learn. Syst., 2021

A Novel, Efficient Implementation of a Local Binary Convolutional Neural Network.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Rescuing RRAM-Based Computing From Static and Dynamic Faults.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Practical Attacks on Deep Neural Networks by Memory Trojaning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Fast Search of the Optimal Contraction Sequence in Tensor Networks.

[BibT_eX]

[DOI]

IEEE J. Sel. Top. Signal Process., 2021

ScaleCert: Scalable Certified Defense against Adversarial Patches with Sparse Superficial Layers.

[BibT_eX]

[DOI]

Proceedings of the Advances in Neural Information Processing Systems 34: Annual Conference on Neural Information Processing Systems 2021, 2021

Cambricon-Q: A Hybrid Architecture for Efficient Training.

[BibT_eX]

[DOI]

Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

Hindsight Value Function for Variance Reduction in Stochastic Dynamic Environment.

[BibT_eX]

[DOI]

Proceedings of the Thirtieth International Joint Conference on Artificial Intelligence, 2021

SpaceA: Sparse Matrix Vector Multiplication on Processing-in-Memory Accelerator.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

SEALing Neural Network Models in Encrypted Deep Learning Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

SemiMap: A Semi-Folded Convolution Mapping for Speed-Overhead Balance on Crossbars.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

NNBench-X: A Benchmarking Methodology for Neural Network Accelerator Designs.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2020

Rethinking the performance comparison between SNNS and ANNS.

[BibT_eX]

[DOI]

Neural Networks, 2020

Tianjic: A Unified and Scalable Chip Bridging Spike-Based and Continuous Neural Computation.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2020

Rubik: A Hierarchical Architecture for Efficient Graph Learning.

[BibT_eX]

[DOI]

CoRR, 2020

SEALing Neural Network Models in Secure Deep Learning Accelerators.

[BibT_eX]

[DOI]

CoRR, 2020

Sequence Triggered Hardware Trojan in Neural Network Accelerator.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

DUET: Boosting Deep Neural Network Efficiency on Dual-Module Architecture.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

HyGCN: A GCN Accelerator with Hybrid Architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

DeepSniffer: A DNN Model Extraction Framework Based on Learning Architectural Hints.

[BibT_eX]

[DOI]

Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019

Neural Network Model Extraction Attacks in Edge Devices by Hearing Architectural Hints.

[BibT_eX]

[DOI]

CoRR, 2019

Programmable Neural Network Trojan for Pre-Trained Feature Extractor.

[BibT_eX]

[DOI]

CoRR, 2019

NNBench-X: Benchmarking and Understanding Neural Network Workloads for Accelerator Designs.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2019

Alleviating Irregularity in Graph Analytics Acceleration: a Hardware/Software Co-Design Approach.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

MEDAL: Scalable DIMM based Near Data Processing Accelerator for DNA Seeding Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Balancing Memory Accesses for Energy-Efficient Graph Analytics Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Dynamic Sparse Graph for Efficient Deep Learning.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Learning Representations, 2019

When Deep Learning Meets the Edge: Auto-Masking Deep Neural Networks for Efficient Machine Learning on Edge Devices.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE International Conference on Computer Design, 2019

Analysis and Optimization of the Memory Hierarchy for Graph Processing Workloads.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

CNNWire: Boosting Convolutional Neural Network with Winograd on ReRAM based Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Memory Trojan Attack on Neural Network Accelerators.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Near-Data Acceleration of Privacy-Preserving Biomarker Search with 3D-Stacked Memory.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Memory-Bound Proof-of-Work Acceleration for Blockchain Applications.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

FPSA: A Full System Stack Solution for Reconfigurable ReRAM-based NN Accelerator Architecture.

[BibT_eX]

[DOI]

Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018

Die Stacking Is Happening.

[BibT_eX]

[DOI]

Xing Hu

Dylan C. Stow

Yuan Xie

IEEE Micro, 2018

Batch Normalization Sampling.

[BibT_eX]

[DOI]

CoRR, 2018

Exploring Core and Cache Hierarchy Bottlenecks in Graph Processing Workloads.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2018

Crossbar-Aware Neural Network Pruning.

[BibT_eX]

[DOI]

IEEE Access, 2018

SCOPE: A Stochastic Computing Engine for DRAM-Based In-Situ Accelerator.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Persistence Parallelism Optimization: A Holistic Approach from Memory Bus to RDMA Network.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

An automated approach to estimating code coverage measures via execution logs.

[BibT_eX]

[DOI]

Zhen Ming (Jack) Jiang

Proceedings of the 33rd ACM/IEEE International Conference on Automated Software Engineering, 2018

RADAR: a 3D-reRAM based DNA alignment accelerator architecture.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

2016

TSocket: Thermal Sustainable Power Budgeting.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2016

2014

Orchestrator: Guarding Against Voltage Emergencies in Multithreaded Applications.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Thermal-Sustainable Power Budgeting for Dynamic Threading.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

SwimmingLane: A composite approach to mitigate voltage droop effects in 3D power delivery network.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Orchestrator: a low-cost solution to reduce voltage emergencies for multi-threaded applications.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2011

A cost-effective substantial-impact-filter based method to tolerate voltage emergencies.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Xing Hu

Timeline

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Bibliography

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