An Inverter-Based True Random Number Generator with 4-bit Von-Neumann Post-Processing Circuit. - Xingyu Wang 002; Hongjie Liu; Ruilin Zhang; Kunyang Liu; Hirofumi Shinohara (MWSCAS, 2020)

36.3 A Modeling Attack Resilient Strong PUF with Feedback-SPN Structure Having <0.73% Bit Error Rate Through In-Cell Hot-Carrier Injection Burn-In. - Kunyang Liu; Zihan Fu; Gen Li; Hongliang Pu; Zhibo Guan; Xingyu Wang 002; Xinpeng Chen; Hirofumi Shinohara (ISSCC, 2021)

A 0.186-pJ per Bit Latch-Based True Random Number Generator with Mismatch Compensation and Random Noise Enhancement. - Ruilin Zhang; Xingyu Wang 002; Luying Wang; Xinpeng Chen; Fan Yang; Kunyang Liu; Hirofumi Shinohara (VLSI Circuits, 2021)

A 0.116pJ/bit Latch-Based True Random Number Generator with Static Inverter Selection and Noise Enhancement. - Xingyu Wang 002; Ruilin Zhang; Yuxin Wang; Kunyang Liu; Xuanzhen Wang; Hirofumi Shinohara (VLSI-DAT, 2022)

A 0.186-pJ per Bit Latch-Based True Random Number Generator Featuring Mismatch Compensation and Random Noise Enhancement. - Ruilin Zhang; Xingyu Wang 002; Kunyang Liu; Hirofumi Shinohara (IEEE J. Solid State Circuits, 2022)

Practical Markov Chain and Von Neumann based Post-processing Circuits for True Random Number Generators. - Ruilin Zhang; Haochen Zhang; Xingyu Wang 002; Ziyang Ye; Kunyang Liu; Hirofumi Shinohara (MWSCAS, 2023)

A 0.116 pJ/bit Latch-Based True Random Number Generator Featuring Static Inverter Selection and Noise Enhancement. - Xingyu Wang 002; Ruilin Zhang; Kunyang Liu; Hirofumi Shinohara (IEEE Trans. Very Large Scale Integr. Syst., 2024)

De-Correlation and De-Bias Post-Processing Circuits for True Random Number Generator. - Ruilin Zhang; Haochen Zhang; Xingyu Wang 002; Ziyang Ye; Kunyang Liu; Shinichi Nishizawa; Kiichi Niitsu; Hirofumi Shinohara (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)