PMPS(3): A Performance Model of Parallel Systems. - Yongran Chen; Xingyun Qi; Yue Qian; Wenhua Dou (Asia-Pacific Computer Systems Architecture Conference, 2006)

A Fault Tolerant Bufferless Optical Interconnection Network. - Xingyun Qi; Quanyou Feng; Yongran Chen; Qiang Dou; Wenhua Dou (ACIS-ICIS, 2009)

BOIN: A novel Bufferless Optical Interconnection Network for high performance computer. - Xingyun Qi; Wei Yang 037; Yongran Chen; Qiang Dou; Quanyou Feng; Wenhua Dou (AICCSA, 2009)

A Scalable and Resilient Microarchitecture Based on Multiport Binding for High-Radix Router Design. - Yi Dai; Kefei Wang; Gang Qu 001; Liquan Xiao; Dezun Dong; Xingyun Qi (IPDPS, 2017)

Optimal Implementation of In-Band Network Management for High-Radix Switches. - Jijun Cao; Mingche Lai; Xingyun Qi; Yi Dai; Zhengbin Pang (ACA, 2020)

MPLEG: A Multi-mode Physical Layer Error Generator for Link Layer Fault Tolerance Test. - Xingyun Qi; Pingjing Lu; Jijun Cao; Yi Dai; Mingche Lai; Junsheng Chang (ACA, 2020)

PFT: A Congestion Avoidance Method based on Proactive Flow Throttling at Endpoints. - Xingyun Qi; Mingche Lai; Dezun Dong; Yi Dai; Junsheng Chang; Jijun Cao (IM, 2021)

MPICC: Multi-Path INT-Based Congestion Control in Datacenter Networks. - Guoyuan Yuan; Dezun Dong; Xingyun Qi; Baokang Zhao (NPC, 2021)

Microarchitecture of a Configurable High-Radix Router for the Post-Moore Era. - Yi Dai; Kai Lu 001; Junsheng Chang; Xingyun Qi; Jijun Cao; Jianmin Zhang (ISC, 2021)

A CNRZ-7 Based Wireline Transceiver With High-Bandwidth-Density, Low-Power for D2D Communication. - Geng Zhang 001; Mingche Lai; Fangxu Lyu; Xuqiang Zheng; Heming Wang; Dongbin Lv; Chaolong Xu; Xingyun Qi; Qing Liu (IEEE Access, 2022)

A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS. - Mingche Lai; Geng Zhang 001; Fangxu Lv; Xuqiang Zheng; Heming Wang; Dongbin Lv; Chaolong Xu; Xingyun Qi (Microelectron. J., 2022)

A reduced complexity MLSD-based adaptive Duo-PAM4 detector in 28-nm CMOS for 56-Gb/s wireline receiver. - Chaolong Xu; Fangxu Lv; Mingche Lai; Zhang Luo; Xingyun Qi; Jiaqing Xu; Qiang Wang 006; Liquan Xiao; Cewen Liu; Hua Xu (A-SSCC, 2024)

Optimization of TDM Using Single-ended Transmission for Multi-FPGA Platforms. - Haoyu Liao; Yuan Li; Puguang Liu; Qiang Wang; Mingche Lai; Xingyun Qi (ISCAS, 2024)

A High-performance Hardware Accelerator for Genome Alignment. - Haoyu Liao; Yuan Li; Qiang Wang; Mingche Lai; Hui Su; Ziwen Li; Xingyun Qi (ISPA, 2024)

Automatic Implementation of Large-Scale CNNs on FPGA Cluster Based on HLS4ML. - Yihang Lu; Xingyun Qi; Yuan Li; Mingche Lai; Yankang Zhao; Zhenqi Li; Hanyuan Li; Qiang Wang (ISPA, 2024)

A Comprehensive Simulation Framework for CXL Disaggregated Memory. - Yanjing Wang 007; Lizhou Wu; Wentao Hong; Yang Ou; Zicong Wang; Sunfeng Gao; Jie Zhang; Sheng Ma; Dezun Dong; Xingyun Qi; Mingche Lai; Nong Xiao (CoRR, 2024)

A low jitter and low reference spur 5GHz PLL with quadrature charge-sampling PD in 28nm CMOS process. - Wenchen Wang; Fangxu Lv; Zhengbin Pang; Heng Huang; Zhang Luo; Xingyun Qi; Jiaqing Xu; Geng Zhang 001; Kewei Xin; Chengzhuo Zhao (IEICE Electron. Express, 2024)

A fully digital timing background calibration algorithm based on first-order auto-correlation for time-interleaved ADCs. - Meng Li; Fangxu Lv; Mingche Lai; Xuqiang Zheng; Heng Huang; Xingyun Qi; Geng Zhang 001 (Microelectron. J., 2024)

A high speed adaptive reflection cancellation equalization circuit with Floating Tap FFE and Loop-Refactored DFE for ADC-DSP-based wireline receiver. - Cewen Liu; Xingyun Qi; Fangxu Lv; Qiang Wang 006; Liquan Xiao; Xiaoyue Hu; Chaolong Xu; Zhouhao Yang; Meng Li; Mingche Lai (Microelectron. J., 2025)

A Novel High-Speed Adaptive Duobinary Digital Detector Based on the Feed-Forward Equalizer and the Maximum Likelihood Sequence Detector for Wireline Transceivers. - Chaolong Xu; Fangxu Lv; Mingche Lai; Xingyun Qi; Qiang Wang 006; Zhang Luo; Shijie Li 002; Geng Zhang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2025)