High-speed VLSI architectures for the AES algorithm. - Xinmiao Zhang 001; Keshab K. Parhi (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Fast factorization architecture in soft-decision Reed-Solomon decoding. - Xinmiao Zhang 001; Keshab K. Parhi (IEEE Trans. Very Large Scale Integr. Syst., 2005)

High-Speed Architectures for Parallel Long BCH Encoders. - Xinmiao Zhang 001; Keshab K. Parhi (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Partial parallel factorization in soft-decision Reed-Solomon decoding. - Xinmiao Zhang 001 (ACM Great Lakes Symposium on VLSI, 2006)

High-speed Factorization Architecture for Soft-decision Reed-Solomon Decoding. - Xinmiao Zhang 001 (ICCD, 2006)

On the Optimum Constructions of Composite Field for the AES Algorithm. - Xinmiao Zhang 001; Keshab K. Parhi (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Reduced Complexity Interpolation Architecture for Soft-Decision Reed-Solomon Decoding. - Xinmiao Zhang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Low-complexity Interpolation Architecture for Soft-decision Reed-Solomon Decoding. - Xinmiao Zhang 001; Jiangli Zhu (ISCAS, 2007)

Efficient Interpolation Architecture for Soft-Decision Reed-Solomon Decoding. - Jiangli Zhu; Xinmiao Zhang 001 (SiPS, 2007)

MONET Special Issue on Next Generation Hardware Architectures for Secure Mobile Computing. - Nicolas Sklavos 001; Máire McLoone; Xinmiao Zhang 001 (Mob. Networks Appl., 2007)

Further Exploring the Strength of Prediction in the Factorization of Soft-Decision Reed-Solomon Decoding. - Xinmiao Zhang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2007)

VLSi architecture design for algebraic soft-decision Reed-Solomon decoding. - Xinmiao Zhang 001 (ACSCC, 2008)

Efficient decoder design for high-throughput LDPC decoding. - Zhiqiang Cui; Zhongfeng Wang 001; Xinmiao Zhang 001; Qingwei Jia (APCCAS, 2008)

Efficient architecture for the Tate pairing in characteristic three. - Qingwei Li; Zhongfeng Wang 001; Xinmiao Zhang 001; Xingcheng Liu (APCCAS, 2008)

Scalable interpolation architecture for soft-decision Reed-Solomon decoding. - Jiangli Zhu; Xinmiao Zhang 001 (APCCAS, 2008)

Combined interpolation architecture for soft-decision decoding of Reed-Solomon codes. - Jiangli Zhu; Xinmiao Zhang 001; Zhongfeng Wang 001 (ICCD, 2008)

FPGA implementation of a factorization processor for soft-decision reed-solomon decoding. - Bainan Chen; Xinmiao Zhang 001 (ISCAS, 2008)

Novel interpolation architecture for Low-Complexity Chase soft-decision decoding of Reed-Solomon codes. - Jiangli Zhu; Xinmiao Zhang 001; Zhongfeng Wang 001 (ISCAS, 2008)

Error correction for multi-level NAND flash memory using Reed-Solomon codes. - Bainan Chen; Xinmiao Zhang 001; Zhongfeng Wang 001 (SiPS, 2008)

Efficient interpolration architecture for soft-decision Reed-Solomon decoding by applying slow-down. - Xinmiao Zhang 001; Jiangli Zhu (SiPS, 2008)

Efficient VLSI Architecture for Soft-Decision Decoding of Reed-Solomon Codes. - Jiangli Zhu; Xinmiao Zhang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

Factorization-free Low-complexity Chase Soft-decision Decoding of Reed-Solomon Codes. - Jiangli Zhu; Xinmiao Zhang 001 (ISCAS, 2009)

Backward Interpolation Architecture for Algebraic Soft-Decision Reed-Solomon Decoding. - Jiangli Zhu; Xinmiao Zhang 001; Zhongfeng Wang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Reduced-latency scheduling scheme for min-max non-binary LDPC decoding. - Xinmiao Zhang 001; Fang Cai (APCCAS, 2010)

High-speed architecture for image reconstruction based on compressive sensing. - Yang Chen; Xinmiao Zhang 001 (ICASSP, 2010)

Partial-parallel decoder architecture for quasi-cyclic non-binary LDPC codes. - Xinmiao Zhang 001; Fang Cai (ICASSP, 2010)

Efficient architecture for generalized minimum-distance decoder of Reed-Solomon codes. - Jiangli Zhu; Xinmiao Zhang 001 (ICASSP, 2010)

High-speed re-encoder design for algebraic soft-decision Reed-Solomon decoding. - Jiangli Zhu; Xinmiao Zhang 001 (ISCAS, 2010)

Hardware complexities of algebraic soft-decision Reed-Solomon decoders and comparisons. - Xinmiao Zhang 001; Jiangli Zhu (ITA, 2010)

High-Throughput Interpolation Architecture for Algebraic Soft-Decision Reed-Solomon Decoding. - Xinmiao Zhang 001; Jiangli Zhu (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Algebraic Soft-Decision Decoder Architectures for Long Reed-Solomon Codes. - Xinmiao Zhang 001; Jiangli Zhu (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

An efficient architecture for iterative soft reliability-based majority-logic non-binary LDPC decoding. - Xinmiao Zhang 001; Fang Cai (ACSCC, 2011)

Low-complexity architectures for reliability-based message-passing non-binary LDPC decoding. - Xinmiao Zhang 001; Fang Cai (ISCAS, 2011)

A novel polynomial selection scheme for low-complexity chase algebraic soft-decision reed-solomon decoding. - Xinmiao Zhang 001; Yingquan Wu; Jiangli Zhu (ISCAS, 2011)

Efficient codeword recovery architecture for low-complexity Chase Reed-Solomon decoding. - Xinmiao Zhang 001; Yu Zheng 011 (ITA, 2011)

Reduced-complexity column-layered decoding and implementation for LDPC codes. - Zhiqiang Cui; Zhongfeng Wang 001; Xinmiao Zhang 001 (IET Commun., 2011)

Reliability-Driven ECC Allocation for Multiple Bit Error Resilience in Processor Cache. - Somnath Paul; Fang Cai; Xinmiao Zhang 001; Swarup Bhunia (IEEE Trans. Computers, 2011)

Efficient Partial-Parallel Decoder Architecture for Quasi-Cyclic Nonbinary LDPC Codes. - Xinmiao Zhang 001; Fang Cai (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Reduced-Complexity Decoder Architecture for Non-Binary LDPC Codes. - Xinmiao Zhang 001; Fang Cai (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Increasing the energy efficiency of WSNs using algebraic soft-decision reed-solomon decoders. - Wei Zhang 055; Xinmiao Zhang 001; Hao Wang 072 (APCCAS, 2012)

A Chase-type Koetter-Vardy algorithm for soft-decision Reed-Solomon decoding. - Xinmiao Zhang 001; Yu Zheng 011; Yingquan Wu (ICNC, 2012)

Phase recovery for QPSK transmission without using complex multipliers. - Xinmiao Zhang 001; Jea Hack Lee; Myung Hoon Sunwoo (ICUIMC, 2012)

Low-power LDPC decoding based on iteration prediction. - Xinmiao Zhang 001; Fang Cai; Richard Shi (ISCAS, 2012)

Low complexity full parallel Multi-Split LDPC decoder reusing sign wire of row processor. - Byung Jun Choi; Jae Do Lee; Myung Hoon Sunwoo; Xinmiao Zhang 001 (ISOCC, 2012)

On the implementation of modified fuzzy vault for biometric encryption. - Xinmiao Zhang 001; Richard Shi; James A. Ritcey (ITA, 2012)

A Low-Complexity Three-Error-Correcting BCH Decoder for Optical Transport Network. - Xinmiao Zhang 001; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Systematically Re-encoded Algebraic Soft-Decision Reed-Solomon Decoder. - Xinmiao Zhang 001; Yu Zheng 011 (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Efficient Reencoder Architectures for Algebraic Soft-Decision Reed-Solomon Decoding. - Xinmiao Zhang 001; Jiangli Zhu; Wei Zhang 055 (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Low-Complexity Reliability-Based Message-Passing Decoder Architectures for Non-Binary LDPC Codes. - Xinmiao Zhang 001; Fang Cai; Shu Lin 001 (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Novel Interpolation and Polynomial Selection for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding. - Xinmiao Zhang 001; Yingquan Wu; Jiangli Zhu; Yu Zheng 011 (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Modified Low-Complexity Chase Soft-Decision Decoder of Reed-Solomon Codes. - Xinmiao Zhang 001; Jiangli Zhu; Wei Zhang 055 (J. Signal Process. Syst., 2012)

Efficient Generalized Minimum-distance Decoders of Reed-Solomon Codes. - Jiangli Zhu; Xinmiao Zhang 001 (J. Signal Process. Syst., 2012)

Low-complexity finite alphabet iterative decoders for LDPC codes. - Fang Cai; Xinmiao Zhang 001; David Declercq; Bane Vasic; Dung Viet Nguyen; Shiva Kumar Planjery (ISCAS, 2013)

Low-energy and low-latency error-correction for phase change memory. - Xinmiao Zhang 001; Fang Cai; M. P. Anantram (ISCAS, 2013)

Low-power design of Reed-Solomon encoders. - Wei Zhang 055; Jing Wang; Xinmiao Zhang 001 (ISCAS, 2013)

Reducing the latency of Lee-O'Sullivan interpolation through modified initialization. - Xinmiao Zhang 001; Richard Shi; James A. Ritcey (ITA, 2013)

An Efficient Interpolation-Based Chase BCH Decoder. - Xinmiao Zhang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

Generalized Backward Interpolation for Algebraic Soft-Decision Decoding of Reed-Solomon Codes. - Xinmiao Zhang 001; Yu Zheng 011 (IEEE Trans. Commun., 2013)

Relaxed Min-Max Decoder Architectures for Nonbinary Low-Density Parity-Check Codes. - Fang Cai; Xinmiao Zhang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2013)

High-speed multi-block-row layered decoding for Quasi-cyclic LDPC codes. - Xinmiao Zhang 001; Ying Tai (GlobalSIP, 2014)

Interpolation-based Chase BCH decoder. - Xinmiao Zhang 001 (ITA, 2014)

Finite Alphabet Iterative Decoders for LDPC Codes: Optimization, Architecture and Analysis. - Fang Cai; Xinmiao Zhang 001; David Declercq; Shiva Kumar Planjery; Bane Vasic (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Efficient Check Node Processing Architectures for Non-binary LDPC Decoding Using Power Representation. - Fang Cai; Xinmiao Zhang 001 (J. Signal Process. Syst., 2014)

Modified trellis-based Min-max decoder for non-binary LDPC codes. - Xinmiao Zhang 001 (ICNC, 2015)

Low-Complexity Modified Trellis-Based Min-Max Non- Binary LDPC Decoders. - Xinmiao Zhang 001 (J. Commun., 2015)

Low-power partial-parallel Chien search architecture with polynomial degree reduction. - Xinmiao Zhang 001; Itai Dror; Sanel Alterman (ISCAS, 2016)

A Flexible and Low-Complexity Local Erasure Recovery Scheme. - Xinmiao Zhang 001; Steven Sprouse; Ishai Ilani (IEEE Commun. Lett., 2016)

Modified Generalized Integrated Interleaved Codes for Local Erasure Recovery. - Xinmiao Zhang 001 (IEEE Commun. Lett., 2017)

Low-Complexity Transformed Encoder Architectures for Quasi-Cyclic Nonbinary LDPC Codes Over Subfields. - Xinmiao Zhang 001; Ying Tai (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Perfect Column-Layered Two-Bit Message-Passing LDPC Decoder and Architectures. - Xinmiao Zhang 001; Alexander Bazarsky (ISCAS, 2018)

Ultra-Compressed Three-Error-Correcting BCH Decoder. - Xinmiao Zhang 001; Michael O'Sullivan (ISCAS, 2018)

Generalized Three-Layer Integrated Interleaved Codes. - Xinmiao Zhang 001 (IEEE Commun. Lett., 2018)

Systematic Encoder of Generalized Three-Layer Integrated Interleaved Codes. - Xinmiao Zhang 001 (ICC, 2019)

Hardware Obfuscation Through Reconfiguration Finite Field Arithmetic Units. - Ankur A Sharma; Xinmiao Zhang 001; Yingjie Lao (ISCAS, 2019)

Hardware Obfuscation of AES through Finite Field Construction Variation. - Xinmiao Zhang 001; Phillip Shvartsman; Jingbo Zhou; Eslam Yahya Tawfik (ISCAS, 2019)

Reducing Parallel Linear Feedback Shift Register Complexity Through Input Tap Modification. - Xinmiao Zhang 001; Yok Jye Tang (ISCAS, 2019)

Decoding of Generalized Three-Layer Integrated Interleaved Codes. - Xinmiao Zhang 001 (ISIT, 2019)

Side Channel Attack Resistant AES Design Based on Finite Field Construction Variation. - Phillip Shvartsman; Xinmiao Zhang 001 (SiPS, 2019)

Relaxing the Constraints on Locally Recoverable Erasure Codes by Finite Field Element Variation. - Xinmiao Zhang 001; Zhenshan Xie (IEEE Commun. Lett., 2019)

On the Construction of Composite Finite Fields for Hardware Obfuscation. - Xinmiao Zhang 001; Yingjie Lao (IEEE Trans. Computers, 2019)

A Low-Power Parallel Architecture for Linear Feedback Shift Registers. - Xinmiao Zhang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Efficient Architectures for Generalized Integrated Interleaved Decoder. - Xinmiao Zhang 001; Zhenshan Xie (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

High-Speed and Low-Complexity Parallel Long BCH Encoder. - Xinmiao Zhang 001 (ISCAS, 2020)

A New Logic-Locking Scheme Resilient to Gate Removal Attack. - Jingbo Zhou; Xinmiao Zhang 001 (ISCAS, 2020)

Efficient Nested Key Equation Solver Architectures for Generalized Integrated Interleaved Codes. - Xinmiao Zhang 001 (ITA, 2020)

Low-Complexity Architectures for Parallel Long BCH Encoders. - Yok Jye Tang; Xinmiao Zhang 001 (SiPS, 2020)

VLSI Architectures for Reed-Solomon Codes: Classic, Nested, Coupled, and Beyond. - Xinmiao Zhang 001 (IEEE Open J. Circuits Syst., 2020)

Scaled Nested Key Equation Solver for Generalized Integrated Interleaved Decoder. - Zhenshan Xie; Xinmiao Zhang 001 (IEEE Trans. Circuits Syst., 2020)

Reduced-Complexity Key Equation Solvers for Generalized Integrated Interleaved BCH Decoders. - Zhenshan Xie; Xinmiao Zhang 001 (IEEE Trans. Circuits Syst., 2020)

Efficient VLSI Architectures for Coupled-Layered Regenerating Codes. - Xinmiao Zhang 001; Zhenshan Xie (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Pipelined High-Throughput NTT Architecture for Lattice-Based Cryptography. - Weihang Tan; Antian Wang; Yingjie Lao; Xinmiao Zhang 001; Keshab K. Parhi (AsianHOST, 2021)

Scaled Fast Nested Key Equation Solver for Generalized Integrated Interleaved BCH Decoders. - Zhenshan Xie; Xinmiao Zhang 001 (ICASSP, 2021)

Reduced-Complexity Modular Polynomial Multiplication for R-LWE Cryptosystems. - Xinmiao Zhang 001; Keshab K. Parhi (ICASSP, 2021)

Low-Complexity Parallel Cyclic Redundancy Check. - Xinmiao Zhang 001; Yok Jye Tang (ISCAS, 2021)

A Low-Complexity Flexible Logic-Locking Scheme Resisting Removal Attacks. - Jingbo Zhou; Xinmiao Zhang 001 (MWSCAS, 2021)

Efficient Architecture for Long Integer Modular Multiplication over Solinas Prime. - Zheang Huai; Keshab K. Parhi; Xinmiao Zhang 001 (SiPS, 2021)

An Efficient Parallel Architecture for Resource-Shareable Reed-Solomon Encoder. - Yok Jye Tang; Xinmiao Zhang 001 (SiPS, 2021)

Low-Latency VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography. - Weihang Tan; Antian Wang; Yingjie Lao; Xinmiao Zhang 001; Keshab K. Parhi (CoRR, 2021)

Miscorrection Mitigation for Generalized Integrated Interleaved BCH Codes. - Zhenshan Xie; Xinmiao Zhang 001 (IEEE Commun. Lett., 2021)

Special Section on Edge AI and Accelerators. - Deepu John; Yongfu Li 002; Xinmiao Zhang 001 (IEEE Open J. Circuits Syst., 2021)

Fast Nested Key Equation Solvers for Generalized Integrated Interleaved Decoder. - Zhenshan Xie; Xinmiao Zhang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Generalized SAT-Attack-Resistant Logic Locking. - Jingbo Zhou; Xinmiao Zhang 001 (IEEE Trans. Inf. Forensics Secur., 2021)

Improved Miscorrection Detection for Generalized Integrated Interleaved BCH Codes. - Zhenshan Xie; Xinmiao Zhang 001 (ICC, 2022)

Efficient Nested Key Equation Solver for Short Generalized Integrated Interleaved BCH Codes. - Zhenshan Xie; Xinmiao Zhang 001 (ISCAS, 2022)

Efficient Check Node Processing for Min-Max NB-LDPC Decoding over Lower-Order Finite Fields. - Xinmiao Zhang 001 (ISCAS, 2022)

Low-Complexity AES Architectures Resilient to Power Analysis Attacks. - Jingbo Zhou; Elsayed Elgendy; Eslam Yahya Tawfik; Xinmiao Zhang 001 (ISCAS, 2022)

Efficient Reconfigurable Vandermonde Matrix Inverter for Erasure-Correcting Generalized Integrated Interleaved Decoding. - Yok Jye Tang; Xinmiao Zhang 001 (SiPS, 2022)

A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures. - Oscar Ferraz; Srinivasan Subramaniyan; Ramesh Chinthala; João Andrade; Joseph R. Cavallaro; Soumitra Kumar Nandy; Vítor Silva 001; Xinmiao Zhang 001; Madhura Purnaprajna; Gabriel Falcão 001 (IEEE Commun. Surv. Tutorials, 2022)

Fast En/Decoding of Reed-Solomon Codes for Failure Recovery. - Yok Jye Tang; Xinmiao Zhang 001 (IEEE Trans. Computers, 2022)

Low-Complexity Resource-Shareable Parallel Generalized Integrated Interleaved Encoder. - Yok Jye Tang; Xinmiao Zhang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Efficient Sub-Codeword Key Equation Solver for Generalized Integrated Interleaved BCH Decoder. - Zhenshan Xie; Xinmiao Zhang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Low-Latency Nested Decoding for Short Generalized Integrated Interleaved BCH Codes. - Zhenshan Xie; Yok Jye Tang; Xinmiao Zhang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Efficient Hardware Implementation Architectures for Long Integer Modular Multiplication over General Solinas Prime. - Zheang Huai; Jingbo Zhou; Xinmiao Zhang 001 (J. Signal Process. Syst., 2022)

Polynomial Multiplication Architecture with Integrated Modular Reduction for R-LWE Cryptosystems. - Xinmiao Zhang 001; Zheang Huai; Keshab K. Parhi (J. Signal Process. Syst., 2022)

Dimensions of Channel Coding: From Theory to Algorithms to Applications. - Tuvi Etzion; Paul H. Siegel; Han Mao Kiah; Hessam Mahdavifar; Farzad Parvaresh; Moshe Schwartz 001; Ido Tal; Eitan Yaakobi; Xinmiao Zhang 001 (IEEE J. Sel. Areas Inf. Theory, 2023)

Fast and Low-Complexity Soft-Decision Generalized Integrated Interleaved Decoder. - Yok Jye Tang; Xinmiao Zhang 001 (IEEE J. Sel. Areas Inf. Theory, 2023)

Algorithmic Obfuscation for LDPC Decoders. - Jingbo Zhou; Xinmiao Zhang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

High-Speed VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography. - Weihang Tan; Antian Wang; Xinmiao Zhang 001; Yingjie Lao; Keshab K. Parhi (IEEE Trans. Computers, 2023)

Sparsity-Aware Medium-Density Parity-Check Decoder for McEliece Cryptosystems. - Xinmiao Zhang 001; Zhenshan Xie (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Joint Protection Scheme for Deep Neural Network Hardware Accelerators and Models. - Jingbo Zhou; Xinmiao Zhang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Low-Complexity Parallel Min-Sum Medium-Density Parity-Check Decoder for McEliece Cryptosystem. - Jiaxuan Cai; Xinmiao Zhang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Improved Ciphertext Multiplication for RNS-CKKS Homomorphic Encryption. - Sajjad Akherati; Xinmiao Zhang 001 (SiPS, 2024)

Low-Complexity Integer Divider Architecture for Homomorphic Encryption. - Sajjad Akherati; Jiaxuan Cai; Xinmiao Zhang 001 (SiPS, 2024)

Low-Latency Parallel Row-Layered Min-sum MDPC Decoder for McEliece Cryptosystem. - Jiaxuan Cai; Xinmiao Zhang 001 (SiPS, 2024)

Highly Efficient Parallel Row-Layered Min-Sum MDPC Decoder for McEliece Cryptosystem. - Jiaxuan Cai; Xinmiao Zhang 001 (CoRR, 2024)

Efficient Homomorphically Encrypted Convolutional Neural Network Without Rotation. - Sajjad Akherati; Xinmiao Zhang 001 (CoRR, 2024)

Generalized Integrated Interleaved Codes for High-Density DRAMs. - Yok Jye Tang; Xinmiao Zhang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Low-Complexity Ciphertext Multiplication for CKKS Homomorphic Encryption. - Sajjad Akherati; Xinmiao Zhang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Hardware Circuits and Systems Design for Post-Quantum Cryptography - A Tutorial Brief. - Jiafeng Xie; Wenfeng Zhao; Hanho Lee; Debapriya Basu Roy; Xinmiao Zhang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Modified Extended Integrated Interleaved Codes. - Yok Jye Tang; Xinmiao Zhang 001 (IEEE Commun. Lett., 2024)

Low-Complexity Parallel Chien Search Architecture Based on Vandermonde Matrix Decomposition. - Yok Jye Tang; Xinmiao Zhang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Guest Editorial Special Issue on the International Symposium on Integrated Circuits and Systems - ISICAS 2024. - Xinmiao Zhang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Guest Editorial Special Issue on the International Symposium on Circuits and Systems - ISCAS 2024. - Xinmiao Zhang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Three-Input Ciphertext Multiplication for Homomorphic Encryption. - Sajjad Akherati; Yok Jye Tang; Xinmiao Zhang 001 (ISCAS, 2025)

Efficient Layered New Bit-Flipping QC-MDPC Decoder for BIKE Post-Quantum Cryptography. - Jiaxuan Cai; Xinmiao Zhang 001 (ISCAS, 2025)

Low-Complexity Linear Feedback Shift Register Architecture For CRC En/Decoding. - Yok Jye Tang; Jiaxuan Cai; Xinmiao Zhang 001 (ISCAS, 2025)

Guest Editorial Special Issue on Emerging Hardware Security and Trust Technologies - AsianHOST 2023. - Xinmiao Zhang 001; Chongyan Gu; Mengmei Ye; Qiang Liu; Reza Azarderakhsh; Weiqiang Liu 001; Yang Li (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)