An energy-efficiency Optimized LEACH-C for wireless sensor networks. - Shuo Shi; Xinning Liu; Xuemai Gu (CHINACOM, 2012)

Date Flow Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications. - Xinning Liu; Chen Mei; Peng Cao 002; Min Zhu 001; Longxing Shi (IEICE Trans. Inf. Syst., 2012)

A GPS Bit Synchronization Method Based on Frequency Compensation. - Xinning Liu; Yuxiang Niu; Jun Yang 006; Peng Cao 002 (IEICE Trans. Commun., 2015)

A harmonic-free cell-based all-digital delay-locked loop for die-to-die clock synchronization of 3-D IC. - Tailong Xu; Feng Xue; Zhikuang Cai; Xinning Liu; Shuo Meng (ASICON, 2017)

HTD: A light-weight holosymmetrical transition detector based in-situ timing monitoring technique for wide-voltage-range in 40nm CMOS. - Wentao Dai; Weiwei Shan; Xinning Liu; Jun Yang 006 (A-SSCC, 2017)

Analytical hold timing fixing for sub-threshold circuit based on its lognormal distribution. - Jingjing Guo; Min Wang; Jizhe Zhu; Xinning Liu; Jun Yang 006 (PATMOS, 2017)

Analytical inverter chain's delay and its variation model for sub-threshold circuits. - Jingjing Guo; Jizhe Zhu; Min Wang; Jianxin Nie; Xinning Liu; Wei Ge; Jun Yang 006 (IEICE Electron. Express, 2017)

An improved timing error prediction monitor for wide adaptive frequency scaling. - Weiwei Shan; Xinning Liu; Minyi Lu; Shuai Shao; Zhikuang Cai; Jun Yang 006 (IEICE Electron. Express, 2017)

Reliability Emphasized MTJ/CMOS Hybrid Circuit Towards Ultra-Low Power. - Hao Cai 001; Menglin Han; You Wang 002; Lirida A. B. Naviner; Xinning Liu; Jun Yang 006; Weisheng Zhao (DCIS, 2018)

MRAM-on-FDSOI Integration: A Bit-Cell Perspective. - Hao Cai 001; You Wang 002; Wang Kang 001; Lirida A. B. Naviner; Xinning Liu; Jun Yang 006; Weisheng Zhao (ISVLSI, 2018)

A Low-Overhead Timing Monitoring Technique for Variation-Tolerant Near-Threshold Digital Integrated Circuits. - Weiwei Shan; Xinning Liu; Minyi Lu; Liang Wan; Jun Yang 006 (IEEE Access, 2018)

Design and Implementation of a Reconfigurable Cryptographic Coprocessor with Multiple Side-Channel Attacks Countermeasures. - Xinchao Shang; Weiwei Shan; Xinning Liu (J. Circuits Syst. Comput., 2018)

A Double Sensing Scheme With Selective Bitline Voltage Regulation for Ultralow-Voltage Timing Speculative SRAM. - Jun Yang 006; Hao Ji; Yichen Guo; Jizhe Zhu; Yuan Zhuang 001; Zhi Li; Xinning Liu; Longxing Shi (IEEE J. Solid State Circuits, 2018)

HTD: A Light-Weight Holosymmetrical Transition Detector for Wide-Voltage-Range Variation Resilient ICs. - Wentao Dai; Weiwei Shan; Xinchao Shang; Xinning Liu; Hao Cai 001; Jun Yang 006 (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A Low Overhead, Within-a-Cycle Adaptive Clock Stretching Circuit With Wide Operating Range in 40-nm CMOS. - Weiwei Shan; Liang Wan; Xinning Liu; Xinchao Shang; Wentao Dai; Shuai Shao; Jun Yang 006; Longxing Shi (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Novel High-speed FPGA-based True Random Number Generator Based on Chaotic Ring Oscillator. - Xinning Liu; Song Jia; Hanzun Zhang (ASICON, 2019)

An embedded implementation of CNN-based hand detection and orientation estimation algorithm. - Li Yang; Zhi Qi; Zeheng Liu; Hao Liu 013; Ming Ling; Longxing Shi; Xinning Liu (Mach. Vis. Appl., 2019)

Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration. - Hao Cai 001; You Wang 002; Lirida Alves de Barros Naviner; Xinning Liu; Weiwei Shan; Jun Yang 006; Weisheng Zhao (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

29.8 115nA@3V ULPMark-CP Score 1205 SCVR-Less Dynamic Voltage-Stacking Scheme for IoT MCU. - Xiaomin Li; Yibo Xu; Lizheng Ren; Weiwei Ge; Jianlong Cai; Xinning Liu; Jun Yang 006 (ISSCC, 2021)

Bit-error-rate aware sensing-error correction interaction in spintronic MRAM. - Hao Cai 001; Xinfang Tong; Pengcheng Wu; Xinning Liu; Bo Liu 019 (J. Syst. Archit., 2022)

SCVR-Less Dynamic Voltage-Stacking Scheme for IoT MCU. - Xinning Liu; Xiaomin Li; Huanqing Zhang; Chenyang Li; Lizheng Ren; Qing Chen; Yibo Xu; Jun Yang 006 (IEEE J. Solid State Circuits, 2022)

Proposal of Analog In-Memory Computing With Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell. - Hao Cai 001; Yanan Guo 004; Bo Liu 019; Mingyang Zhou 002; Juntong Chen; Xinning Liu; Jun Yang 006 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

An efficient path delay variability model for wide-voltage-range digital circuits. - Weiwei Shan; Yuqiang Cui; Wentao Dai; Xinning Liu; Jingjing Guo; Peng Cao 002; Jun Yang 006 (Sci. China Inf. Sci., 2023)

Association Analysis and Cross-Selling Strategy for Sports Products Based on Apriori and K-means Algorithms. - Tianxia Xie; Xinning Liu; Yingjie He (ICCBD, 2024)

22 nm Ultra-Low Power MCU with 43.5nW/KB Sleep Retention Power for Automotive Grade-1 Applications. - Yibo Liu; Wen Wang; Hongjin Zhu; Longning Qi; Bo Liu 019; Xinning Liu; Jun Yang 006; Hao Cai 001 (ICTA, 2024)

34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs. - An Guo 001; Xi Chen 107; Fangyuan Dong; Jinwu Chen; Zhihang Yuan; Xing Hu 010; Yuanpeng Zhang; Jingmin Zhang; Yuchen Tang; Zhican Zhang; Gang Chen 023; Dawei Yang; et al. (ISSCC, 2024)

14.6 A 28nm 64kb Bit-Rotated Hybrid-CIM Macro with an Embedded Sign-Bit-Processing Array and a Multi-Bit-Fusion Dual-Granularity Cooperative Quantizer. - Xi Chen 107; Shaochen Li; Zhican Zhang; Wentao Zheng; Xiao Tan; Yuchen Tang; Yuhui Shi; Lizheng Ren; Yibo Mai; Feiran Liu; Jinwu Chen; Zhaoyang Zhang; et al. (ISSCC, 2025)

14.7 NeuroPilot: A 28nm, 69.4fJ/node and 0.22ns/node, 32×32 Mimetic-Path-Searching CIM-Macro with Dynamic-Logic Pilot PE and Dual-Direction Searching. - An Guo 001; Jingmin Zhang; Xingyu Pu; Yi Yang 001; Defa Wu; Yuchen Tang; Yuhui Shi; Yinghai Gao; Zhichao Liu; Bo Wang 023; Tianzhu Xiong; Zhaoyang Zhang; et al. (ISSCC, 2025)