Low Overhead Online Checkpoint for Intermittently Powered Non-volatile FPGAs. - Xinyi Zhang 001; Clay Patterson; Yongpan Liu; Chengmo Yang; Chun Jason Xue; Jingtong Hu (ISVLSI, 2018)

Accuracy vs. Efficiency: Achieving Both through FPGA-Implementation Aware Neural Architecture Search. - Weiwen Jiang; Xinyi Zhang 001; Edwin Hsing-Mean Sha; Lei Yang 018; Qingfeng Zhuge; Yiyu Shi 001; Jingtong Hu (DAC, 2019)

XFER: A Novel Design to Achieve Super-Linear Performance on Multiple FPGAs for Real-Time AI. - Weiwen Jiang; Xinyi Zhang 001; Edwin Hsing-Mean Sha; Qingfeng Zhuge; Lei Yang 018; Yiyu Shi 001; Jingtong Hu (FPGA, 2019)

When Neural Architecture Search Meets Hardware Implementation: from Hardware Awareness to Co-Design. - Xinyi Zhang 001; Weiwen Jiang; Yiyu Shi 001; Jingtong Hu (ISVLSI, 2019)

Achieving Super-Linear Speedup across Multi-FPGA for Real-Time DNN Inference. - Weiwen Jiang; Edwin H.-M. Sha; Xinyi Zhang 001; Lei Yang 018; Qingfeng Zhuge; Yiyu Shi 001; Jingtong Hu (ACM Trans. Embed. Comput. Syst., 2019)

Achieving Full Parallelism in LSTM via a Unified Accelerator Design. - Xinyi Zhang 001; Weiwen Jiang; Jingtong Hu (ICCD, 2020)

Low Overhead Online Data Flow Tracking for Intermittently Powered Non-Volatile FPGAs. - Xinyi Zhang 001; Clay Patterson; Yongpan Liu; Chengmo Yang; Chun Jason Xue; Jingtong Hu (ACM J. Emerg. Technol. Comput. Syst., 2020)

DAC-SDC Low Power Object Detection Challenge for UAV Applications. - Xiaowei Xu 004; Xinyi Zhang 001; Bei Yu 001; Xiaobo Sharon Hu; Christopher Rowen; Jingtong Hu; Yiyu Shi 001 (IEEE Trans. Pattern Anal. Mach. Intell., 2021)

Algorithm-hardware Co-design of Attention Mechanism on FPGA Devices. - Xinyi Zhang 001; Yawen Wu; Peipei Zhou 001; Xulong Tang; Jingtong Hu (ACM Trans. Embed. Comput. Syst., 2021)

H2H: heterogeneous model to heterogeneous system mapping with computation and communication awareness. - Xinyi Zhang 001; Cong Hao; Peipei Zhou 001; Alex K. Jones; Jingtong Hu (DAC, 2022)

FPIRM: Floating-point Processing in Racetrack Memories. - Sébastien Ollivier; Xinyi Zhang 001; Yue Tang 002; Chayanika Choudhuri; Jingtong Hu; Alex K. Jones (CoRR, 2022)

Pod-racing: bulk-bitwise to floating-point compute in racetrack memory for machine learning at the edge. - Sébastien Ollivier; Xinyi Zhang 001; Yue Tang 002; Chayanika Choudhuri; Jingtong Hu; Alex K. Jones (IEEE Micro, 2022)

EF-Train: Enable Efficient On-device CNN Training on FPGA through Data Reshaping for Online Adaptation or Personalization. - Yue Tang 002; Xinyi Zhang 001; Peipei Zhou 001; Jingtong Hu (ACM Trans. Design Autom. Electr. Syst., 2022)