A 4-GS/s 8-bit two-channel time-interleaved folding and interpolating ADC. - Fan Jiang; DanYu Wu; Lei Zhou 014; Jin Wu; Zhi Jin; Xinyu Liu 004 (Sci. China Inf. Sci., 2014)

A 30Gsps 6bit DAC in SiGe BiCMOS technology. - Lei Zhou 014; Weizhong Li; DanYu Wu; Fan Jiang; Daojun Xue; Jin Wu; Xinyu Liu 004 (ICECS, 2016)

A four-channel time-interleaved 30-GS/s 6-bit ADC in 0.18 μm SiGe BiCMOS technology. - Xiaoge Zhu; DanYu Wu; Lei Zhou 014; Yinkun Huang; Jin Wu; Xinyu Liu 004 (Sci. China Inf. Sci., 2017)

A 6 mW 325 MS/s 8 bit SAR ADC with background offset calibration. - Xiaoge Zhu; DanYu Wu; Lei Zhou 014; Chonghe Ma; Dandan Wang; Jian Luan 002; Yinkun Huang; Jin Wu; Xinyu Liu 004 (IEICE Electron. Express, 2017)

A 400-MS/s 10-b 8 interleaved SAR ADC in 0.13 um CMOS. - Xiaoge Zhu; Lei Zhou 014; DanYu Wu; Jin Wu; Xinyu Liu 004 (IEICE Electron. Express, 2017)

A 112-Gb/s PAM-4 Transmitter With a 2-Tap Fractional-Spaced FFE in 65-nm CMOS. - Hao Ding; Xuqiang Zheng; DanYu Wu; Lei Zhou 014; Jin Wu; Fangxu Lv; Jianye Wang; Xinyu Liu 004 (ESSCIRC, 2019)

A 10-GS/s 8-bit SiGe ADC with Isolated 4×4 Analog Input Multiplexer. - DanYu Wu; Lei Zhou 014; Huasen Liu; Yinkun Huang; Jian Luan 002; Xuan Guo; Jin Wu; Xinyu Liu 004 (ISCAS, 2019)

A 10-GS/s 8-bit 4-way interleaved folding ADC in 0.18 µm SiGe-BiCMOS. - Huasen Liu; DanYu Wu; Lei Zhou 014; Yinkun Huang; Jian Luan 002; Xuan Guo; Dong Wang 033; Xuqiang Zheng; Jin Wu; Xinyu Liu 004 (IEICE Electron. Express, 2019)

A 1 GS/s 12-bit pipelined folding ADC with a novel encoding algorithm. - Huasen Liu; DanYu Wu; Lei Zhou 014; Jian Luan 002; Xuan Guo; Dong Wang 033; Jin Wu; Xinyu Liu 004 (IEICE Electron. Express, 2019)

An 8 GSps 14 bit RF DAC With IM3<-62 dBc up to 3.6 GHz. - Dong Wang 033; Lei Zhou 014; DanYu Wu; Chonghe Ma; Jinxin Xue; Xuan Guo; Jian Luan 002; Huasen Liu; Jin Wu; Xinyu Liu 004 (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 50-112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS. - Xuqiang Zheng; Hao Ding; Feng Zhao 004; DanYu Wu; Lei Zhou 014; Jin Wu; Fangxu Lv; Jianye Wang; Xinyu Liu 004 (IEEE J. Solid State Circuits, 2020)

Frequency-Domain Modeling and Analysis of Injection-Locked Oscillators. - Xuqiang Zheng; Fangxu Lv; Lei Zhou 014; DanYu Wu; Jin Wu; Chun Zhang; Woogeun Rhee; Xinyu Liu 004 (IEEE J. Solid State Circuits, 2020)

A Real-Time Output 50-GS/s 8-bit TI-ADC with Dedicated Calibration Techniques and Deterministic Latency. - Jian Luan 002; Danyu Wu; Xuqiang Zheng; Chen Cai; Linzhen Wu; Lei Zhou 014; Jin Wu; Xinyu Liu 004 (ESSCIRC, 2021)

A 1.4-Vppd 64-Gb/s PAM-4 Transmitter with 4-Tap Hybrid FFE Employing Fractionally-Spaced Pre-Emphasis and Baud-Spaced De-Emphasis in 28-nm CMOS. - Chen Cai; Xuqiang Zheng; Yong Chen 005; Danyu Wu; Jian Luan 002; Lei Zhou 014; Jin Wu; Xinyu Liu 004 (ESSCIRC, 2021)

A 64Gbps 1.36 Vppd 1.44pJ/b Fully CMOS-Style Transmitter with Active Hybrid Driver in 28nm CMOS. - Da Fu; Danyu Wu; Xuan Guo; Hanbo Jia; Jie Fu; Shan Lu; Xinyu Liu 004 (MWSCAS, 2023)

A 1-GS/s 12-bit Single-Channel Pipelined ADC in 28-nm CMOS With Input-Split Fully Differential Ring Amplifier. - Heng Zhang 037; Ben He; Xuan Guo; Danyu Wu; Xinyu Liu 004 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A wideband front-end with integrated high-voltage assisted input buffer for high-speed ADC. - Zilin Jiang; Danyu Wu; Xuan Guo; Hanbo Jia; Shuangbao Jia; Heping Ma; Kai Sun; Xinyu Liu 004 (IEICE Electron. Express, 2024)

A 1.25-GS/s 14-bit pipelined ADC using a current-feedback flipped input buffer and large dither technique to achieve high linearity. - Zeyu Li; Xuan Guo; Hanbo Jia; Xinyu Liu 004 (IEICE Electron. Express, 2024)

A 1.25-GS/s 10-bit single-channel ring amplifier-based pipelined ADC in 28-nm CMOS. - Heng Zhang 037; Xuan Guo; Ben He; Hanbo Jia; Xinyu Liu 004 (Microelectron. J., 2024)

A 12bit 1.6 GS/s pipelined ADC with multi-level dither injection achieving 68 dB SFDR over PVT. - Feitong Wu; Hanbo Jia; Xuan Guo; Zilin Jiang; Xinyu Liu 004 (Microelectron. J., 2024)

A 28-nm Dual-Mode Explicit Class-F₂₃ VCO With Low-Loss CM Return Path Achieving 70-400-kHz 1/f³ PN Corner Over 4.9-7.3-GHz TR. - Shan Lu; Danyu Wu; Xuan Guo; Hanbo Jia; Yong Chen 005; Xinyu Liu 004 (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A 16-Bit 5 GS/s DAC With Redundant-MSB-Based Digital Pre-Distortion Achieving SFDR >61 dBc Up to 2.4 GHz in 40-nm CMOS. - Xing Li; Lei Zhou 014; Xuan Guo; Hanbo Jia; Danyu Wu; Jin Wu; Xinyu Liu 004 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 500MS/s 14-bit Pipelined ADC With Startup Protection Circuit in 40 nm CMOS. - Ben He; Xuan Guo; Hanbo Jia; Kai Sun; Xinyu Liu 004 (IEEE Access, 2025)

A dither-based background calibration circuit for pipelined ADCs in 40 nm CMOS. - Ben He; Xuan Guo; Hanbo Jia; Kai Sun; Lei Zhou 014; Zhijie Chen; Xinyu Liu 004 (IEICE Electron. Express, 2025)

An input buffer with opamp-based bootstrap circuit and cross-coupled substrate technique for 1.5-GS/s pipelined ADC in 40-nm CMOS process. - Zeyu Li; Fangyuan Xu; Xuan Guo; Hanbo Jia; Kai Sun; Xinyu Liu 004 (IEICE Electron. Express, 2025)

A high-speed single channel reconfigurable 1-GS/s to 1.5-GS/s, 8-bit to 6-bit SAR ADC in 28 nm CMOS. - Qing Su; Xuan Guo; Hanbo Jia; Yihan Li; Kai Sun; Xinyu Liu 004 (IEICE Electron. Express, 2025)

A 100 Gb/s PAM4 receiver analog front-end with 33.1-dB boost in 28-nm CMOS process. - Qiuyue Zhang; Xuqiang Zheng; Fangxu Lv; Wenxiang Zhen; Mingche Lai; Zhi Jin; Xinyu Liu 004 (IEICE Electron. Express, 2025)

A 14-GS/s 8-bit time-interleaved SAR ADC with multi-path bootstrapped switch and low-jitter sampling PLL in 28-nm CMOS. - Jiawei Ding; Xuan Guo; Shan Lu; Qing Su; Tao liu; Hanbo Jia; Yihan Li; Xinyu Liu 004 (Microelectron. J., 2025)

A 100-MHz bandwidth continuous-time sigma-delta ADC with 1 V supply in 28 nm CMOS. - Ben He; Xuan Guo; Hanbo Jia; Xinyu Liu 004 (Microelectron. J., 2025)

A 500 MS/s 12b single channel SAR-assisted pipelined ADC with two-stage open-loop dynamic amplifier. - Qing Su; Xuan Guo; Hanbo Jia; Heping Ma; Linzhen Wu; Kai Sun; Xinyu Liu 004 (Microelectron. J., 2025)

A genetic algorithm-based capacitor mismatch calibration scheme for SAR ADCs. - Yuzhen Zhang; Xuan Guo; Hanbo Jia; Li Luo; Linzhen Wu; Dandan Wang; Xinyu Liu 004 (Microelectron. J., 2025)

A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Utilizing a Complementary-Injection Scheme and an Adaptive Pulsewidth Adjustment. - Zedong Wang; Xuqiang Zheng; Yu He; Hua Xu; Sai Li; Zunsong Yang; Fangxu Lv; Mingche Lai; Xinyu Liu 004 (IEEE J. Solid State Circuits, 2025)

A Quad-Core VCO Incorporating Area-Saving Folded S-Shaped Tail Filtering in 28-nm CMOS. - Shan Lu; Danyu Wu; Xuan Guo; Hanbo Jia; Yong Chen 005; Xinyu Liu 004 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A Depletion-Mode GaN-Based Envelope Tracking Supply Modulator Utilizing a Novel Coupled PWM Generator. - Chenhao Li; Chunyue Bo; Xiaoyu Hu; Xiangcong Zhai; Ke Wei; Xinyu Liu 004; Weijun Luo (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A 25-GS/s 8-bit Current-Steering DAC With ADC-Based Duty-Cycle Detection in 40-nm CMOS. - Xing Li; Lei Zhou 014; Xuan Guo; Hanbo Jia; Danyu Wu; Jin Wu; Xinyu Liu 004 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A 112-Gb/s PAM-4 Retimer Transceiver With Jitter-Filtering Clocking Scheme and BER Optimization Technique in 28-nm CMOS. - Hua Xu; Mingche Lai; Xuqiang Zheng; Zedong Wang; Jiang Xu; Sai Li; Fangxu Lv; Min Liu; Weijie Li; Zhanhao Wen; Xuan Guo; Xinhua Wang; et al. (IEEE J. Solid State Circuits, 2025)