A 224-Gb/s PAM4 High-Linearity, Energy-Efficiency Differential to Single-Ended Driver in 130-nm SiGe BiCMOS. - Jiahan Fu; Pingyi Cai; Xiongshi Luo; Xuewei You; Liping Zhong; Wenbo Xiao; Fujiang Lin; Yao Li; Quan Pan 002 (ICTA, 2020)

Fully-Differential 100-Gb/s PAM4 Cross-Coupled Regulated Transimpedance Amplifier. - Dongfan Xu; Zhang Qiu; Xiongshi Luo; Xuewei You; Wenbo Xiao; Siqiang Zhu; Minzhe Tang; Zhenghao Li; Quan Pan 002 (ICTA, 2020)

A Low-Power PAM4 Receiver With an Adaptive Variable-Gain Rectifier-Based Decoder. - Quan Pan 002; Li Wang 083; Xiongshi Luo; C. Patrick Yue (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A 720-mVpp 224-Gb/s PAM4 Optical Receiver with Multiple Peaking Techniques in 130-nm SiGe BiCMOS. - Qi Zhang; Xiongshi Luo; Zhenghao Li; Dongfan Xu; Siqiang Zhu; Leiming Wang; Zhenjiang Mao; Xiaoyan Gui; Dan Li 011; Hongyu Yu; Quan Pan 002 (APCCAS, 2021)

A 160-Gb/s 0.37-pJ/bit PAM4 Optical Receiver in 28-nm CMOS. - Leiming Wang; Xiongshi Luo; Dongfan Xu; Zhang Qiu; Yiyang Yan; Quan Pan 002 (APCCAS, 2022)

A 112-Gb/s Single-Ended PAM-4 Transceiver Front-End for Reach Extension in Long-Reach Link. - Xiongshi Luo; Xuewei You; Jiahan Fu; Zhenghao Li; Liping Zhong; Taiyang Fan; Zhang Qiu; Wenbo Xiao; Yong Chen 005; Quan Pan 002 (ESSCIRC, 2022)

A 2×50Gb/s Single-Ended MIMO PAM-4 Crosstalk Cancellation and Signal Reutilization Receiver in 28 nm CMOS. - Liping Zhong; Hongzhi Wu; Weitao Wu; Wenbo Xiao; Xiongshi Luo; Dongfan Xu; Xuxu Cheng; Zhenghao Li; Taiyang Fan; Quan Pan 002 (ESSCIRC, 2022)

A 2 x 24Gb/s Single-Ended Transceiver with Channel-Independent Encoder-Based Crosstalk Cancellation in 28nm CMOS. - Hongzhi Wu; Weitao Wu; Liping Zhong; Xuxu Cheng; Xiongshi Luo; Zhenghao Li; Dongfan Xu; Quan Pan 002 (A-SSCC, 2023)

A 28-Gb/s PAM-4 Fully-Integrated Optical Receiver with High-Speed Silicon Photodetector in 28-nm CMOS. - Dongshen Zhan; Liping Zhong; Wentao Zhou; Zhenyu Yao; Xiongshi Luo; Yangyi Zhang; Hemiao Wang; De Zhou; Quan Pan 002 (ICTA, 2023)

A Fully-Integrated LDO with Two-Stage Cross-Coupled Error Amplifier for High-Speed Communications in 28-nm CMOS. - Dongfan Xu; Yangyi Zhang; Zhenghao Li; Xiongshi Luo; Pingyi Cai; Hongzhi Wu; Liping Zhong; Weitao Wu; Liru Zhu; Quan Pan 002 (ISCAS, 2023)

A 0.96-0.9-V Fully Integrated FVF LDO With Two-Stage Cross-Coupled Error Amplifier. - Dongfan Xu; Yangyi Zhang; Xiongshi Luo; Zhenghao Li; Quan Pan 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 128Gb/s PAM-4 Transmitter with Edge-Boosting Pulse Generator and Pre-Emphasis Asymmetric Fractional-Spaced FFE in 28nm CMOS. - Hongzhi Wu; Weitao Wu; Liping Zhong; Xuxu Cheng; Yangyi Zhang; Xiongshi Luo; Dongfan Xu; Xindan Yu; Quan Pan 002 (CICC, 2024)

7.5 A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE. - Xiongshi Luo; Xuewei You; Zhenghao Li; Hamed Mosalam; Dongfan Xu; Taiyang Fan; Hongchang Qiao; Wentao Zhou; Hongzhi Wu; Liping Zhong; Patrick Yin Chiang; Quan Pan 002 (ISSCC, 2024)

13.5 A 64Gb/s/pin PAM4 Single-Ended Transmitter with a Merged Pre-Emphasis Capacitive-Peaking Crosstalk-Cancellation Scheme for Memory Interfaces in 28nm CMOS. - Weitao Wu; Hongzhi Wu; Liping Zhong; Xuxu Cheng; Xiongshi Luo; Dongfan Xu; Catherine Wang; Zhenghao Li; Quan Pan 002 (ISSCC, 2024)

7.6 A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS. - Liping Zhong; Hongzhi Wu; Yangyi Zhang; Xuxu Cheng; Weitao Wu; Catherine Wang; Xiongshi Luo; Taiyang Fan; Dongfan Xu; Quan Pan 002 (ISSCC, 2024)

A 2x112 Gb/s 0.34 pJ/b/Lane Single-Ended PAM4 Receiver with Multi-Order Crosstalk Cancellation and Signal Reutilization Technique in 28-nm CMOS. - Liping Zhong; Yangyi Zhang; Xiongshi Luo; Hongzhi Wu; Xuxu Cheng; Weitao Wu; Zhenghao Li; Quan Pan 002 (VLSI Technology and Circuits, 2024)

A 2×56 Gb/s 0.78-pJ/b PAM-4 Crosstalk Cancellation Receiver With Active Crosstalk Extraction Technique in 28-nm CMOS. - Liping Zhong; Hongzhi Wu; Weitao Wu; Catherine Wang; Wenbo Xiao; Xiongshi Luo; Yangyi Zhang; Dongfan Xu; Wei Wang 433; Taiyang Fan; Zhenghao Li; Xuxu Cheng; et al. (IEEE J. Solid State Circuits, 2024)

A 0.3-to-10.1 GHz 33.8fSRMS-Jitter Hybrid Injection-Locked Eight-Phase Clock Generator with Adaptive Mismatch Cancellation Technique for High-Speed Links in 28nm CMOS. - Hongzhi Wu; Xuxu Cheng; Liping Zhong; Yangyi Zhang; Weitao Wu; Xiongshi Luo; Quan Pan 002 (CICC, 2025)

36.6 A 112Gb/s 0.61pJ/b PAM-4 Linear TIA Supporting Extended PD-TIA Reach in 28nm CMOS. - Yangyi Zhang; Zhenyu Yao; Wentao Zhou; Xiongshi Luo; Zhenghao Li; Dongshen Zhan; Quan Pan 002 (ISSCC, 2025)

A 64 Gb/s/pin Single-Ended PAM-4 Transmitter With a Merged Preemphasis Capacitive-Peaking Crosstalk Cancellation Scheme for Memory Interfaces in 28-nm CMOS. - Weitao Wu; Hongzhi Wu; Liping Zhong; Xuxu Cheng; Xiongshi Luo; Dongfan Xu; Catherine Wang; Zhenghao Li; Quan Pan 002 (IEEE J. Solid State Circuits, 2025)

A 2 × 112 Gb/s/pin Single-Ended Crosstalk Cancellation Transceiver With 31-dB Loss Compensation in 28-nm CMOS. - Liping Zhong; Hongzhi Wu; Yangyi Zhang; Xuxu Cheng; Weitao Wu; Catherine Wang; Xiongshi Luo; Taiyang Fan; Dongfan Xu; Zhenghao Li; Quan Pan 002 (IEEE J. Solid State Circuits, 2025)

A 2 × 24 Gb/s Single-Ended Transceiver With Channel-Independent Encoder-Based Crosstalk Cancellation in 28-nm CMOS. - Hongzhi Wu; Liping Zhong; Weitao Wu; Catherine Wang; Xuxu Cheng; Xiongshi Luo; Yangyi Zhang; Dongfan Xu; Quan Pan 002 (IEEE J. Solid State Circuits, 2025)