An Effective Detailed Routing Algorithm Considering Advanced VLSI Technologies. - Peng Zou; Xiqiong Bai; Yingjie Wu; Lifeng Wu; Jianli Chen (ASICON, 2019)

Unified Contamination-Aware Routing Method Considering Realistic Washing Capacity Constraint in Digital Microfluidic Biochips. - Zhipeng Huang 009; Xiqiong Bai; Tingshen Lan; Xingquan Li; Geng Lin (IEEE Access, 2020)

Late Breaking Results: Heterogeneous Circuit Layout Centerline Extraction for Mask Verification. - Xiqiong Bai; Ziran Zhu; Peng Zou; Lichong Sun; Jianli Chen (DAC, 2021)

Voronoi Diagram Based Heterogeneous Circuit Layout Centerline Extraction for Mask Verification. - Xiqiong Bai; Ziran Zhu; Peng Zou; Jianli Chen; Jun Yu 010; Yao-Wen Chang (ASP-DAC, 2022)

Timing-Aware Fill Insertions With Design-Rule and Density Constraints. - Xiqiong Bai; Ziran Zhu; Pingping Li; Jianli Chen; Tingshen Lan; Xingquan Li; Jun Yu 010; Wenxing Zhu; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A fast and high-performance global router with enhanced congestion control. - Xiqiong Bai; Yilu Chen; Zhifeng Lin; Min Wei; Zhijie Cai; Ziran Zhu; Jianli Chen (Integr., 2024)

High-correlation 3D routability estimation for congestion-guided global routing. - Yilu Chen; Miaodi Su; Hongzhi Ding; Shaohong Weng; Zhifeng Lin; Xiqiong Bai (J. Supercomput., 2024)

Network-Architecture-Aware Multiplexer Decomposition for Technology Mapping. - Yilu Chen; Zhifeng Lin; Xiaojian Liang; Zhijie Cai; Xiqiong Bai; Jianli Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Analytical Layer Assignment with Simulated Annealing Refinement. - Zhijie Cai; Min Wei; Peng Zou; Xiqiong Bai; Zhifeng Lin; Jianli Chen (ISCAS, 2025)