A 65nm 8b-Activation 8b-Weight SRAM-Based Charge-Domain Computing-in-Memory Macro Using A Fully-Parallel Analog Adder Network and A Single-ADC Interface. - Guodong Yin; Mufeng Zhou; Yiming Chen; Wenjun Tang; Zekun Yang; Mingyen Lee; Xirui Du; Jinshan Yue; Jiaxin Liu; Huazhong Yang; Yongpan Liu; Xueqing Li 002 (CoRR, 2022)

SAMBA: Single-ADC Multi-Bit Accumulation Compute-in-Memory Using Nonlinearity- Compensated Fully Parallel Analog Adder Tree. - Yiming Chen; Guodong Yin; Mufeng Zhou; Wenjun Tang; Zekun Yang; Mingyen Lee; Xirui Du; Jinshan Yue; Jiaxin Liu; Huazhong Yang; Yongpan Liu; Xueqing Li 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 28nm 166.9 TOPS/W x Mb/mm2 DRAM-Free QLC Compute-in-ROM Macro Supporting High Task-Level Inference Energy Efficiency for Tiny AI Edge Devices. - Ling-An Cheong; Chen Wang; Mufeng Zhou; Tianyu Liao; Mingyen Lee; Yue Ke; Wenjun Tang; Yiming Chen; Xirui Du; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (A-SSCC, 2024)

A 28nm 8928Kb/mm2-Weight-Density Hybrid SRAM/ROM Compute-in-Memory Architecture Reducing >95% Weight Loading from DRAM. - Guodong Yin; Yiming Chen; Mingyen Lee; Xirui Du; Yue Ke; Wenjun Tang; Zhonghao Chen; Mufeng Zhou; Jinshan Yue; Huazhong Yang; Hongyang Jia; Yongpan Liu; et al. (CICC, 2024)

Cramming More Weight Data Onto Compute-in-Memory Macros for High Task-Level Energy Efficiency Using Custom ROM With 3984-kb/mm2 Density in 65-nm CMOS. - Guodong Yin; Yiming Chen; Mufeng Zhou; Wenjun Tang; Mingyen Lee; Zekun Yang; Tianyu Liao; Xirui Du; Vijaykrishnan Narayanan; Huazhong Yang; Hongyang Jia; Yongpan Liu; et al. (IEEE J. Solid State Circuits, 2024)

3D-METRO: Deploy Large-Scale Transformer Model on A Chip Using Transistor-Less 3D-Metal-ROM-Based Compute-in-Memory Macro. - Yiming Chen; Xirui Du; Guodong Yin; Wenjun Tang; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (ASP-DAC, 2025)