SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs. - Yi-Hsiang Lai; Hongbo Rong; Size Zheng 001; Weihao Zhang; Xiuping Cui; Yunshan Jia; Jie Wang 022; Brendan Sullivan; Zhiru Zhang; Yun Liang 001; Youhui Zhang; Jason Cong; et al. (ICCAD, 2020)

A Mapping Model of SNNs to Neuromorphic Hardware. - Xiuping Cui; Xiaochen Hao; Yun Liang 001; Guangyu Sun 003; Xiaoxin Cui; Yuan Wang 001; Ru Huang 001 (AICAS, 2022)

ARES: A Mapping Framework of DNNs Towards Diverse PIMs with General Abstractions. - Xiuping Cui; Size Zheng 001; Tianyu Jia; Le Ye; Yun Liang 001 (ICCAD, 2023)

PAICORE: A 1.9-Million-Neuron 5.181-TSOPS/W Digital Neuromorphic Processor With Unified SNN-ANN and On-Chip Learning Paradigm. - Yi Zhong; Yisong Kuang; Kefei Liu 002; Zilin Wang; Shuo Feng; Guang Chen; Youming Yang 002; Xiuping Cui; Qiankun Wang; Jian Cao 002; Song Jia; Yun Liang 001; et al. (IEEE J. Solid State Circuits, 2025)

MoQa: Rethinking MoE Quantization with Multi-stage Data-model Distribution Awareness. - Zihao Zheng; Xiuping Cui; Size Zheng 001; Maoliang Li; Jiayu Chen; Yun (Eric) Liang; Xiang Chen (CoRR, 2025)

FedHQ: Hybrid Runtime Quantization for Federated Learning. - Zihao Zheng; Ziyao Wang; Xiuping Cui; Maoliang Li; Jiayu Chen; Yun Liang 001; Ang Li; Xiang Chen (CoRR, 2025)