Multi retention level STT-RAM cache designs with a dynamic refresh scheme. - Zhenyu Sun 001; Xiuyuan Bi; Hai (Helen) Li; Weng-Fai Wong; Zhong-Liang Ong; Xiaochun Zhu; Wenqing Wu (MICRO, 2011)

Spintronic memristor based temperature sensor design with CMOS current reference. - Xiuyuan Bi; Chao Zhang 007; Hai Li 001; Yiran Chen 001; Robinson E. Pino (DATE, 2012)

Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches. - Xiuyuan Bi; Zhenyu Sun 001; Hai Li 001; Wenqing Wu (ICCAD, 2012)

Process variation aware data management for STT-RAM cache design. - Zhenyu Sun 001; Xiuyuan Bi; Hai Li 001 (ISLPED, 2012)

Analysis and Optimization of Thermal Effect on STT-RAM Based 3-D Stacked Cache Design. - Xiuyuan Bi; Hai Li 001; Jae-Joon Kim (ISVLSI, 2012)

STT-RAM designs supporting dual-port accesses. - Xiuyuan Bi; Mohamed Anis Weldon; Hai Li 001 (DATE, 2013)

Unleashing the potential of MLC STT-RAM caches. - Xiuyuan Bi; Mengjie Mao; Danghui Wang; Hai Li 001 (ICCAD, 2013)

A pseudo-weighted sensing scheme for memristor based cross-point memory. - Zhijie Chen; Lu Zhang; Xiuyuan Bi; Hai Li 001 (NANOARCH, 2013)

Optimizing MLC-based STT-RAM caches by dynamic block size reconfiguration. - Jianxing Wang; Pooja Roy; Weng-Fai Wong; Xiuyuan Bi; Hai Li 001 (ICCD, 2014)

Design exploration of racetrack lower-level caches. - Zhenyu Sun 001; Xiuyuan Bi; Alex K. Jones; Hai Li 001 (ISLPED, 2014)

STT-RAM Cache Hierarchy With Multiretention MTJ Designs. - Zhenyu Sun 001; Xiuyuan Bi; Hai Li 001; Weng-Fai Wong; Xiaochun Zhu (IEEE Trans. Very Large Scale Integr. Syst., 2014)

An efficient STT-RAM-based register file in GPU architectures. - Xiaoxiao Liu 001; Mengjie Mao; Xiuyuan Bi; Hai Li 001; Yiran Chen 001 (ASP-DAC, 2015)

The evolutionary spintronic technologies and their usage in high performance computing. - Hai (Helen) Li; Xiuyuan Bi; Zhenyu Sun 001 (SoCC, 2015)

Design and Implementation of a 4Kb STT-MRAM with Innovative 200nm Nano-ring Shaped MTJ. - Zheng Li; Xiuyuan Bi; Hai (Helen) Li; Yiran Chen 001; Jianying Qin; Peng Guo; Wenjie Kong; Wenshan Zhan; Xiufeng Han; Hong Zhang; Lingling Wang; Guanping Wu; et al. (ISLPED, 2016)

Array Organization and Data Management Exploration in Racetrack Memory. - Zhenyu Sun 001; Xiuyuan Bi; Wenqing Wu; Sungjoo Yoo; Hai (Helen) Li (IEEE Trans. Computers, 2016)

Cross-Layer Optimization for Multilevel Cell STT-RAM Caches. - Xiuyuan Bi; Mengjie Mao; Danghui Wang; Hai Helen Li (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Exploring Applications of STT-RAM in GPU Architectures. - Xiaoxiao Liu 001; Mengjie Mao; Xiuyuan Bi; Hai Helen Li; Yiran Chen 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)