Verification of logic control design using SIPN and model checking: methods and case study. - Xiying Weng; Lothar Litz (ACC, 2000)

Model checking of signal interpreted Petri nets. - Xiying Weng; Lothar Litz (SMC, 2001)

Controller design for an FMS using Signal Interpreted Petri Nets and SFC: Validation of both descriptions via model-checking. - Stéphane Klein; Xiying Weng; Georg Frey; Jean-Jacques Lesage; Lothar Litz (ACC, 2002)

Model checking: towards generating a correct specification for logic controllers. - Xiying Weng; Lothar Litz (ACC, 2002)

Verification and validation of logic control algorithms by model checking. - Xiying Weng (2003)