Design of Compact and High speed, Totally Self Checking CMOS Checkers for m-out-of-n Codes. - Xrysovalantis Kavousianos; Dimitris Nikolos; G. Sidiropoulos (DFT, 1997)

Self-exercising self testing k-order comparators. - Xrysovalantis Kavousianos; Dimitris Nikolos (VTS, 1997)

Novel Single and Double Output TSC Berger Code Checkers. - Xrysovalantis Kavousianos; Dimitris Nikolos (VTS, 1998)

Low Power Dissipation in BIST Schemes for Modified Booth Multipliers. - Xrysovalantis Kavousianos; Dimitris Bakalis; Haridimos T. Vergos; Dimitris Nikolos; George Alexiou (DFT, 1999)

Modular TSC Checkers for Bose-Lin and Bose Codes. - Xrysovalantis Kavousianos; Dimitris Nikolos (VTS, 1999)

New efficient totally self-checking Berger code checkers. - Xrysovalantis Kavousianos; Dimitris Nikolos; G. Foukarakis; T. Gnardellis (Integr., 1999)

Test response compaction by an accumulator behaving as a multiple input non-linear feedback shift register. - Xrysovalantis Kavousianos; Dimitris Bakalis; Dimitris Nikolos (ITC, 2000)

Novel Single and Double Output TSC CMOS Checkers for m-out-of-n Codes. - Xrysovalantis Kavousianos; Dimitris Nikolos; G. Sidiropoulos (VLSI Design, 2000)

Σχεδίαση αυτοελεγχόμενων ελεγκτών σε τεχνολογία VLSI - Xrysovalantis Kavousianos (2000)

A novel reseeding technique for accumulator-based test pattern generation. - Xrysovalantis Kavousianos; Dimitris Bakalis; Dimitris Nikolos (ACM Great Lakes Symposium on VLSI, 2001)

A New Reseeding Technique for LFSR-Based Test Pattern Generation. - Emmanouil Kalligeros; Xrysovalantis Kavousianos; Dimitris Bakalis; Dimitris Nikolos (IOLTW, 2001)

On the Design of Self-Testing Checkers for Modified Berger Codes. - Stanislaw J. Piestrak; Dimitris Bakalis; Xrysovalantis Kavousianos (IOLTW, 2001)

On Accumulator-Based Bit-Serial Test Response Compaction Schemes. - Dimitris Bakalis; Dimitris Nikolos; Haridimos T. Vergos; Xrysovalantis Kavousianos (ISQED, 2001)

Low Power Built-In Self-Test Schemes for Array and Booth Multipliers. - Dimitris Bakalis; Xrysovalantis Kavousianos; Haridimos T. Vergos; Dimitris Nikolos; G. Ph. Alexiou (VLSI Design, 2001)

A ROMless LFSR Reseeding Scheme for Scan-based BIST. - Emmanouil Kalligeros; Xrysovalantis Kavousianos; Dimitris Nikolos (Asian Test Symposium, 2002)

An Efficient Seeds Selection Method for LFSR-Based Test-per-Clock BIST. - Emmanouil Kalligeros; Xrysovalantis Kavousianos; Dimitris Bakalis; Dimitris Nikolos (ISQED, 2002)

On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST. - Emmanouil Kalligeros; Xrysovalantis Kavousianos; Dimitris Bakalis; Dimitris Nikolos (J. Electron. Test., 2002)

A new built-in TPG method for circuits with random patternresistant faults. - Xrysovalantis Kavousianos; Dimitris Bakalis; Dimitris Nikolos; Spyros Tragoudas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

A highly regular multi-phase reseeding technique for scan-based BIST. - Emmanouil Kalligeros; Xrysovalantis Kavousianos; Dimitris Nikolos (ACM Great Lakes Symposium on VLSI, 2003)

Virtual-scan: a novel approach for software-based self-testing of microprocessors. - Giorgos Dimitrakopoulos; Xrysovalantis Kavousianos; Dimitris Nikolos (ISCAS (5), 2003)

DV-TSE: Difference Vector Based Test Set Embedding. - Maciej Bellos; Xrysovalantis Kavousianos; Dimitris Nikolos; Dimitri Kagaris (VLSI-SOC, 2003)

Low Power Testing by Test Vector Ordering with Vector Repetition. - Maciej Bellos; Dimitris Bakalis; Dimitris Nikolos; Xrysovalantis Kavousianos (ISQED, 2004)

An Efficient Test Vector Ordering Method for Low Power Testing. - Xrysovalantis Kavousianos; Dimitris Bakalis; Maciej Bellos; Dimitris Nikolos (ISVLSI, 2004)

Multiphase BIST: a new reseeding technique for high test-data compression. - Emmanouil Kalligeros; Xrysovalantis Kavousianos; Dimitris Nikolos (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Power aware test-data compression for scan-based testing. - George Gekas; Dimitris Nikolos; Emmanouil Kalligeros; Xrysovalantis Kavousianos (ICECS, 2005)

Reseeding-Based Test Set Embedding with Reduced Test Sequences. - Emmanouil Kalligeros; D. Kaseridis; Xrysovalantis Kavousianos; Dimitris Nikolos (ISQED, 2005)

Efficient test-data compression for IP cores using multilevel Huffman coding. - Xrysovalantis Kavousianos; Emmanouil Kalligeros; Dimitris Nikolos (DATE, 2006)

Efficient Multiphase Test Set Embedding for Scan-based Testing. - Emmanouil Kalligeros; Xrysovalantis Kavousianos; Dimitris Nikolos (ISQED, 2006)

Optimal Selective Huffman Coding for Test-Data Compression. - Xrysovalantis Kavousianos; Emmanouil Kalligeros; Dimitris Nikolos (IEEE Trans. Computers, 2007)

Multilevel Huffman Coding: An Efficient Test-Data Compression Method for IP Cores. - Xrysovalantis Kavousianos; Emmanouil Kalligeros; Dimitris Nikolos (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

State Skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP Cores. - Vasileios Tenentes; Xrysovalantis Kavousianos; Emmanouil Kalligeros (DATE, 2008)

Timing Error Detection and Correction by Time Dilation. - Andreas Floros 003; Yiorgos Tsiatouhas; Xrysovalantis Kavousianos (VLSI-SoC (Selected Papers), 2008)

Test Data Compression Based on Variable-to-Variable Huffman Encoding With Codeword Reusability. - Xrysovalantis Kavousianos; Emmanouil Kalligeros; Dimitris Nikolos (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Multilevel-Huffman Test-Data Compression for IP Cores With Multiple Scan Chains. - Xrysovalantis Kavousianos; Emmanouil Kalligeros; Dimitris Nikolos (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Generation of compact test sets with high defect coverage. - Xrysovalantis Kavousianos; Krishnendu Chakrabarty (DATE, 2009)

LFSR-based test-data compression with self-stoppable seeds. - M. Koutsoupia; Emmanouil Kalligeros; Xrysovalantis Kavousianos; Dimitris Nikolos (DATE, 2009)

Efficient partial scan cell gating for low-power scan-based testing. - Xrysovalantis Kavousianos; Dimitris Bakalis; Dimitris Nikolos (ACM Trans. Design Autom. Electr. Syst., 2009)

Defect Coverage-Driven Window-Based Test Compression. - Xrysovalantis Kavousianos; Krishnendu Chakrabarty; Emmanouil Kalligeros; Vasileios Tenentes (Asian Test Symposium, 2010)

Defect aware X-filling for low-power scan testing. - S. Balatsouka; Vasileios Tenentes; Xrysovalantis Kavousianos; Krishnendu Chakrabarty (DATE, 2010)

Self-Freeze Linear Decompressors for Low Power Testing. - Vasileios Tenentes; Xrysovalantis Kavousianos (ISVLSI, 2010)

Self-Freeze Linear Decompressors: Test Pattern Generators for Low Power Scan Testing. - Vasileios Tenentes; Xrysovalantis Kavousianos (ISVLSI (Selected papers), 2010)

Single and Variable-State-Skip LFSRs: Bridging the Gap Between Test Data Compression and Test Set Embedding for IP Cores. - Vasileios Tenentes; Xrysovalantis Kavousianos; Emmanouil Kalligeros (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Test Scheduling for Multicore SoCs with Dynamic Voltage Scaling and Multiple Voltage Islands. - Xrysovalantis Kavousianos; Krishnendu Chakrabarty; Arvind Jain; Rubin A. Parekhji (Asian Test Symposium, 2011)

Low Power Test-Compression for High Test-Quality and Low Test-Data Volume. - Vasileios Tenentes; Xrysovalantis Kavousianos (Asian Test Symposium, 2011)

Signature Analysis for Testing, Diagnosis, and Repair of Multi-mode Power Switches. - Zhaobo Zhang; Xrysovalantis Kavousianos; Yan Luo; Yiorgos Tsiatouhas; Krishnendu Chakrabarty (ETS, 2011)

Test-data volume and scan-power reduction with low ATE interface for multi-core SoCs. - Vasileios Tenentes; Xrysovalantis Kavousianos (ICCAD, 2011)

A BIST scheme for testing and repair of multi-mode power switches. - Zhaobo Zhang; Xrysovalantis Kavousianos; Yiorgos Tsiatouhas; Krishnendu Chakrabarty (IOLTS, 2011)

A Robust and Reconfigurable Multi-mode Power Gating Architecture. - Zhaobo Zhang; Xrysovalantis Kavousianos; Krishnendu Chakrabarty; Yiorgos Tsiatouhas (VLSI Design, 2011)

Generation of Compact Stuck-At Test Sets Targeting Unmodeled Defects. - Xrysovalantis Kavousianos; Krishnendu Chakrabarty (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Defect-Oriented LFSR Reseeding to Target Unmodeled Defects Using Stuck-at Test Sets. - Xrysovalantis Kavousianos; Vasileios Tenentes; Krishnendu Chakrabarty; Emmanouil Kalligeros (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Time-division multiplexing for testing SoCs with DVS and multiple voltage islands. - Xrysovalantis Kavousianos; Krishnendu Chakrabarty; Arvind Jain; Rubin A. Parekhji (ETS, 2012)

Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands. - Xrysovalantis Kavousianos; Krishnendu Chakrabarty; Arvind Jain; Rubin A. Parekhji (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Testing for SoCs with advanced static and dynamic power-management capabilities. - Xrysovalantis Kavousianos; Krishnendu Chakrabarty (DATE, 2013)

High-Quality Statistical Test Compression With Narrow ATE Interface. - Vasileios Tenentes; Xrysovalantis Kavousianos (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Multi-site test optimization for multi-Vdd SoCs using space- and time- division multiplexing. - Fotis Vartziotis; Xrysovalantis Kavousianos; Krishnendu Chakrabarty; Rubin A. Parekhji; Arvind Jain (DATE, 2014)

Recent advances in single- and multi-site test optimization for DVS-based SoCs. - Xrysovalantis Kavousianos; Krishnendu Chakrabarty (DTIS, 2014)

The Time Dilation Technique for Timing Error Tolerance. - Stefanos Valadimas; Andreas Floros 003; Yiorgos Tsiatouhas; Angela Arapoyanni; Xrysovalantis Kavousianos (IEEE Trans. Computers, 2014)

Built-In Self-Test, Diagnosis, and Repair of MultiMode Power Switches. - Ran Wang 002; Zhaobo Zhang; Xrysovalantis Kavousianos; Yiorgos Tsiatouhas; Krishnendu Chakrabarty (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches. - Zhaobo Zhang; Xrysovalantis Kavousianos; Krishnendu Chakrabarty; Yiorgos Tsiatouhas (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A branch-&-bound algorithm for TAM optimization in multi-Vdd SoCs. - Fotios Vartziotis; Xrysovalantis Kavousianos; Krishnendu Chakrabarty (ETS, 2015)

Test-access-mechanism optimization for multi-Vdd SoCs. - Fotios Vartziotis; Xrysovalantis Kavousianos; Panagiotis Georgiou; Krishnendu Chakrabarty (ITC, 2015)

Time-Division Multiplexing for Testing DVFS-Based SoCs. - Fotis Vartziotis; Xrysovalantis Kavousianos; Krishnendu Chakrabarty; Arvind Jain; Rubin A. Parekhji (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Two-dimensional time-division multiplexing for 3D-SoCs. - Panagiotis Georgiou; Fotios Vartziotis; Xrysovalantis Kavousianos; Krishnendu Chakrabarty (ETS, 2016)

Critical path - Oriented & thermal aware X-filling for high un-modeled defect coverage. - Fotios Vartziotis; Xrysovalantis Kavousianos (DATE, 2017)

A Branch-&-Bound Test-Access-Mechanism Optimization Method for Multi-Vdd SoCs. - Fotis Vartziotis; Xrysovalantis Kavousianos; Panagiotis Georgiou; Krishnendu Chakrabarty (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Fault-Independent Test-Generation for Software-Based Self-Testing. - Panagiotis Georgiou; Xrysovalantis Kavousianos; Riccardo Cantoro; Matteo Sonza Reorda (IOLTS, 2018)

Testing 3D-SoCs Using 2-D Time-Division Multiplexing. - Panagiotis Georgiou; Fotis Vartziotis; Xrysovalantis Kavousianos; Krishnendu Chakrabarty (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

K3 TAM Optimization for Testing 3D-SoCs using Non-Regular Time-Division-Multiplexing. - Panagiotis Georgiou; Iakovos Theodosopoulos; Xrysovalantis Kavousianos (ETS, 2019)