Xu Cheng

According to our database1, Xu Cheng authored at least 53 papers between 2005 and 2017.

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Bibliography

2017
Content Look-Aside Buffer for Redundancy-Free Virtual Disk I/O and Caching.
Proceedings of the 13th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2017

Prediction of distribution network malfunction based on meteorological factors.
Proceedings of the 13th International Conference on Natural Computation, 2017

Understanding the I/O Behavior of Desktop Applications in Virtualization.
Proceedings of the Computing Frontiers Conference, 2017

Locality-aware bank partitioning for shared DRAM MPSoCs.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

A Staged Memory Resource Management Method for CMP systems.
Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017

2016
MFAP: Fair Allocation between fully backlogged and non-fully backlogged applications.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

vSIP: virtual scheduler for interactive performance.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

2015
An Energy-Efficient Branch Prediction with Grouped Global History.
Proceedings of the 44th International Conference on Parallel Processing, 2015

Exploration of the Relationship Between Just-in-Time Compilation Policy and Number of Cores.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2015

2014
Retention Benefit Based Intelligent Cache Replacement.
J. Comput. Sci. Technol., 2014

SPTU: Improving Dynamic Binary Translation through Software Prediction with Target Updating.
Proceedings of the International Conference on Systems and Storage, 2014

Block value based insertion policy for high performance last-level caches.
Proceedings of the 2014 International Conference on Supercomputing, 2014

Improving system throughput and fairness simultaneously in shared memory CMP systems via Dynamic Bank Partitioning.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

DTT: program structure-aware indirect branch optimization via direct-TPC-table in DBT system.
Proceedings of the Computing Frontiers Conference, CF'14, 2014

2013
Page policy control with memory partitioning for DRAM performance and power efficiency.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

An energy-efficient branch prediction technique via global-history noise reduction.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

2012
SWIP Prediction: Complexity-Effective Indirect-Branch Prediction Using Pointers.
J. Comput. Sci. Technol., 2012

Affinity-aware DMA buffer management for reducing off-chip memory access.
Proceedings of the ACM Symposium on Applied Computing, 2012

Reducing last level cache pollution through OS-level software-controlled region-based partitioning.
Proceedings of the ACM Symposium on Applied Computing, 2012

CVP: an energy-efficient indirect branch prediction with compiler-guided value pattern.
Proceedings of the International Conference on Supercomputing, 2012

Improving inclusive cache performance with two-level eviction priority.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Energy-efficient branch prediction with Compiler-guided History Stack.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Optimal bypass monitor for high performance last-level caches.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011
Dynamic Memory Demand Estimating Based on the Guest Operating System Behaviors for Virtual Machines.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2011

TAP prediction: Reusing conditional branch predictor for indirect branches with Target Address Pointers.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

2010
Research Progress of UniCore CPUs and PKUnity SoCs.
J. Comput. Sci. Technol., 2010

TERA: A FPGA-based trace-driven emulation framework for designing on-chip communication architectures.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Energy efficient management scheme for heterogeneous secondary storage system in mobile computers.
Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), 2010

Bit-level optimization for high-level synthesis and FPGA-based acceleration.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

FPGA prototyping of an amba-based windows-compatible SoC.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

FEMU: a firmware-based emulation framework for SoC verification.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

A customized design of DRAM controller for on-chip 3D DRAM stacking.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

A 3D SoC design for H.264 application with on-chip DRAM stacking.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009
PaS: A Preemption-aware Scheduling Interface for Improving Interactive Performance in Consolidated Virtual Machine Environment.
Proceedings of the 15th IEEE International Conference on Parallel and Distributed Systems, 2009

A Heterogeneous Auto-offloading Framework Based on Web Browser for Resource-Constrained Devices.
Proceedings of the Fourth International Conference on Internet and Web Applications and Services, 2009

WHOLE: A low energy I-Cache with separate way history.
Proceedings of the 27th International Conference on Computer Design, 2009

Track Down HW Function Faults Using Real SW Invariants.
Proceedings of the CSIE 2009, 2009 WRI World Congress on Computer Science and Information Engineering, March 31, 2009

2008
CASA: A New IFU Architecture for Power-Efficient Instruction Cache and TLB Designs.
J. Comput. Sci. Technol., 2008

Analysis and Enhancement for Interactive-Oriented Virtual Machine Scheduling.
Proceedings of the 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), 2008

Super-K: A SoC for single-chip ultra mobile computer.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
An Energy-Efficient Instruction Scheduler Design with Two-Level Shelving and Adaptive Banking.
J. Comput. Sci. Technol., 2007

A Fast and Efficient Codec for Multimedia Applications in Wireless Thin-Client Computing.
Proceedings of the 2007 International Symposium on a World of Wireless, 2007

Efficient code size reduction without performance loss.
Proceedings of the 2007 ACM Symposium on Applied Computing (SAC), 2007

Unichos: a full system simulator for thin client platform.
Proceedings of the 2007 ACM Symposium on Applied Computing (SAC), 2007

NISD: A Framework for Automatic Narrow Instruction Set Design.
Proceedings of the Embedded Software and Systems, [Third] International Conference, 2007

Reuse Distance Based Cache Leakage Control.
Proceedings of the High Performance Computing, 2007

A Fast Lossless Codec of Continuous-Tone Images for Thin Client Computing.
Proceedings of the 2007 Data Compression Conference (DCC 2007), 2007

Clock domain crossing fault model and coverage metric for validation of SoC design.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

A Retargetable Software Timing Analyzer Using Architecture Description Language.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

GISP: A Transparent Superpage Support Framework for Linux.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006
A Low Complexity MPEG Video Decoder with Arbitrary Downscaling Capability.
Proceedings of the 2006 4th Workshop on Embedded Systems for Real-Time Multimedia, 2006

2005
Non-interleaving architecture for hardware implementation of modular multiplication.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

BluePower - A New Distributed Multihop Scatternet Formation Protocol for Bluetooth Networks.
Proceedings of the 34th International Conference on Parallel Processing (ICPP 2005), 2005


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