Modeling of a double-sampling switched-capacitor bandpass delta-sigma modulator for multi-standard applications. - Hong Chang; Wenxian Lu; Xu Cheng 002; Yawei Guo; Xiaoyang Zeng (ASICON, 2011)

A multi-mode 1-V DAC+filter in 65-nm CMOS for reconfigurable (GSM, TD-SCDMA and WCDMA) transmitters. - Li Li 038; Jun Ma 005; Yawei Guo; Xu Cheng 002; Xiaoyang Zeng (ASICON, 2011)

A low power 10-bit 100-MS/s SAR ADC in 65nm CMOS. - Jun Ma 005; Yawei Guo; Li Li 038; Yue Wu; Xu Cheng 002; Xiaoyang Zeng (ASICON, 2011)

A low power 1.0 GHz VCO in 65nm-CMOS LP-process. - Zhang Zhang 004; Zhiyi Yu; Xu Cheng 002; Xiaoyang Zeng (ASICON, 2011)

A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS. - Jun Han 003; Xingxing Zhang; Yi Li; Baoyu Xiong; Yuejun Zhang; Zhang Zhang 004; Zhiyi Yu; Xu Cheng 002; Xiaoyang Zeng (IEICE Electron. Express, 2012)

An extensible and real-time compressive sensing reconstruction hardware for WBANs using OMP. - Weijing Shi; Yi Li; Jun Han 003; Xu Cheng 002; Xiaoyang Zeng (ASICON, 2013)

A 1.8-V 14-bit inverter-based incremental ΣΔ ADC for CMOS image sensor. - Biao Wang; Meng Zhang; Xu Cheng 002; Qi Feng; Xiaoyang Zeng (ASICON, 2013)

A highly energy-efficient compressed sensing encoder with robust subthreshold clockless pipeline for wireless BANs. - Yi Li; Xu Cheng 002; Yicheng Zhang; Weijing Shi; Jun Han 003; Xiaoyang Zeng (BioCAS, 2013)

A split-capacitor vcm-based capacitor-switching scheme for low-power SAR ADCs. - Yue Wu; Xu Cheng 002; Xiaoyang Zeng (ISCAS, 2013)

A 960 μW 10-bit 70-MS/s SAR ADC with an energy-efficient capacitor-switching scheme. - Yue Wu; Xu Cheng 002; Xiaoyang Zeng (Microelectron. J., 2013)

An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing. - Yi Li; Liang Wen; Yuejun Zhang; Xu Cheng 002; Jun Han 003; Zhiyi Yu; Xiaoyang Zeng (IEICE Electron. Express, 2014)

A 16-Core Processor With Shared-Memory and Message-Passing Communications. - Zhiyi Yu; Ruijin Xiao; Kaidi You; Heng Quan; Peng Ou; Zheng Yu 001; Maofei He; Jiajie Zhang; Yan Ying; Haofan Yang 001; Jun Han 003; Xu Cheng 002; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Non-binary digital calibration for split-capacitor DAC in SAR ADC. - Yawei Guo; Yue Wu; Dongdong Guo; Xu Cheng 002; Zhiyi Yu; Xiaoyang Zeng (IEICE Electron. Express, 2015)

Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process. - Xiaoyang Zeng; Yi Li; Yuejun Zhang; Shujie Tan; Jun Han 003; Xingxing Zhang; Zhang Zhang 004; Xu Cheng 002; Zhiyi Yu (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Analysis and improvement of ramp gain error in single-ramp single-slope ADCs for CMOS image sensors. - Xu Cheng 002; Xiaoyang Zeng; Qi Feng (Microelectron. J., 2016)

Subthreshold Level Shifter With Self-Controlled Current Limiter by Detecting Output Error. - Liang Wen; Xu Cheng 002; Shudong Tian; Haibo Wen; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier. - Liang Wen; Xu Cheng 002; Keji Zhou; Shudong Tian; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A 24-bit sigma-delta ADC with configurable chopping scheme. - Li Li 038; Xu Cheng 002; Zhang Zhang 004; Jianmin Zeng; Xiaoyang Zeng (IEICE Electron. Express, 2019)

Exploring a Bayesian Optimization Framework Compatible with Digital Standard Flow for Soft-Error-Tolerant Circuit. - Yan Li 084; Xiaoyoung Zeng; Zhengqi Gao; Liyu Lin; Jun Tao 001; Jun Han 003; Xu Cheng 002; Mehdi B. Tahoori; Xiaoyang Zeng (DAC, 2020)

Design Methodology of Clock Polarity Inversion Technique for Frequency Dividers. - Xu Cheng 002; Jue Wang; Jun Han 003; Xiaoyang Zeng (ISCAS, 2020)

A Synthesis Friendly VCO-Based Delta-Sigma ADC with Process Variation Tolerance. - Jue Wang; Xu Cheng 002; Jun Han 003; Xiaoyang Zeng (ISCAS, 2020)

A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application. - Yan Li 084; Xu Cheng 002; Chiyu Tan; Jun Han 003; Yuanfu Zhao; Liang Wang 024; Tongde Li; Mehdi B. Tahoori; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

VPQC: A Domain-Specific Vector Processor for Post-Quantum Cryptography Based on RISC-V Architecture. - Guozhu Xin; Jun Han 003; Tianyu Yin; Yuchao Zhou; Jianwei Yang; Xu Cheng 002; Xiaoyang Zeng (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Radiation-Hardened 0.3-0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications. - Yuanyuan Han; Xu Cheng 002; Jun Han 003; Xiaoyang Zeng (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A 0.9V Supply 12.5Gb/s LVDS Receiver in 28nm CMOS Process. - Jinrong Li; Jue Wang; Xu Cheng 002; Yicheng Zeng; Xiaoyang Zeng (ASICON, 2021)

A High-Efficient and Configurable Hardware Accelerator for Convolutional Neural Network. - Hui Zhang; Zhaojie Li; Heqing Yang; Xu Cheng 002; Xiaoyang Zeng (ASICON, 2021)

A Synthesizable 0.0060mm2 VCO-Based Delta Sigma Modulator with Digital Tri-level Feedback Scheme. - Jue Wang; Zhenyu Yang; Jiawei Wang; Xu Cheng 002; Jun Han 003; Xiaoyang Zeng (A-SSCC, 2021)

Synthesizable lead-lag quantization technique for digital VCO-based ΔΣ ADC. - Jue Wang; Xu Cheng 002; Jun Han 003; Xiaoyang Zeng (Microelectron. J., 2021)

An energy-efficient crypto-extension design for RISC-V. - Weizhen Wang; Jun Han 003; Xu Cheng 002; Xiaoyang Zeng (Microelectron. J., 2021)

A 28 nm, 397 μW real-time dynamic gesture recognition chip based on RISC-V processor. - Yong-Liang Zhang; Qiang Li; Hui Zhang; Wei-Zhen Wang; Jun Han 003; Xiaoyang Zeng; Xu Cheng 002 (Microelectron. J., 2021)

Radiation Hardened 12T SRAM With Crossbar-Based Peripheral Circuit in 28nm CMOS Technology. - Yuanyuan Han; Tongde Li; Xu Cheng 002; Liang Wang 024; Jun Han 003; Yuanfu Zhao; Xiaoyang Zeng (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework. - Chiyu Tan; Yan Li 084; Xu Cheng 002; Jun Han 003; Xiaoyang Zeng (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

An Improved Multi-Objective Optimization Framework for Soft-Error Immune Circuits. - Shaohang Chu; Yan Li 084; Xu Cheng 002; Xiaoyang Zeng (APCCAS, 2022)

A Fully Synthesizable Dynamic Latched Comparator with Reduced Kickback Noise. - Min Li; Jue Wang; Xu Cheng 002; Xiaoyang Zeng (ISCAS, 2022)

A Cross Regulation Reduced Multi-Output and Multi-VCR Piezoelectric Energy Harvesting System Using Shared Capacitors. - Jing Wang 220; Zhiyuan Chen 002; Junrui Liang; Xu Cheng 002; Jun Han 003; Xiaoyang Zeng (ISCAS, 2022)

A Synthesis Friendly Dynamic Amplifier with Fuzzy-Logic Piecewise-Linear Calibration. - Jiawei Wang; Jue Wang; Xu Cheng 002; Jun Han 003; Xiaoyang Zeng (ISCAS, 2022)

An Enhanced Start-up Circuit Eliminating All Trojan States in Self-biased Reference Generators. - Baijie Zhang; Jue Wang; Xu Cheng 002; Jun Han 003; Xiaoyang Zeng (ISCAS, 2022)

A Self Bias-flip Piezoelectric Energy Harvester Array without External Energy Reservoirs achieving 488% Improvement with 4-Ratio Switched-PEH DC-DC Converter. - Zhen Li; Zhiyuan Chen 002; Man-Kay Law; Sijun Du; Xu Cheng 002; Xiaoyang Zeng; Jun Han 003 (CICC, 2023)

A foreground digital calibration algorithm for time-interleaved ADCs with low computational complexity. - Song Wang; Xu Cheng 002; Ziyu Guo; Jun Han 003 (Microelectron. J., 2023)

A Non-Redundant Latch With Key-Node-Upset Obstacle of Beneficial Efficiency for Harsh Environments Applications. - Yan Liu; Yan Li 084; Xu Cheng 002; Jun Han 003; Xiaoyang Zeng (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

DMBF: Design Metrics Balancing Framework for Soft-Error-Tolerant Digital Circuits Through Bayesian Optimization. - Yan Li 084; Chao Chen; Xu Cheng 002; Jun Han 003; Xiaoyang Zeng (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Dominant-Node Theory and Monitoring-Rescue Method for Eliminating Undesired Operating Points in the Self-Biased Reference Generators. - Baijie Zhang; Jiawei Wang; Xu Cheng 002; Jun Han 003; Xiaoyang Zeng (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

An Energy-Efficient BNN Accelerator With Two-Stage Value Prediction for Sparse-Edge Gesture Recognition. - Yongliang Zhang; Yitong Rong; Xuyang Duan; Zhen Yang; Qiang Li; Ziyu Guo; Xu Cheng 002; Xiaoyang Zeng; Jun Han 003 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

SET Tolerable SRAM Hardened by DMR Circuit With Feedback-Split-Gate Voter and High-Speed Hierarchical Structure. - Yuanyuan Han; Xu Cheng 002; Xiaoyong Xue; Jun Han 003; Jiawei Xu 001; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 1.6 GS/s 42.6-dB SNDR Synthesis Friendly Time-Interleaved SAR ADC Using Metastability Detection and Escape Acceleration Technique. - Jiawei Wang; Zhao Gao; Xu Cheng 002; Jue Wang; Zhen Li; Jun Han 003; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Piezoelectric Energy Harvesting Interface Using Self-Bias-Flip Rectifier and Switched-PEH DC-DC for MPPT. - Zhen Li; Jing Wang 220; Man-Kay Law; Sijun Du; Junrui Liang; Xu Cheng 002; Jun Han 003; Xiaoyang Zeng; Zhiyuan Chen 002 (IEEE J. Solid State Circuits, 2024)

Penta Interlocking Dual Ports 14T SRAM with Inside-Bit interleaving Layout Isolation for Soft Error Recovery. - Xu Luo; Yuanyuan Han; Xu Cheng 002; Xiaoyang Zeng (ISCAS, 2025)

Background Calibration for Mixed Mismatches in TIADC Using Taylor-Volterra-Series-Based Model. - Song Wang; Xu Cheng 002; Ziyu Guo; Jun Han 003 (ISCAS, 2025)