ESL design and multi-core validation using the System-on-Chip Environment. - Weiwei Chen 001; Xu Han 002; Rainer Dömer (HLDVT, 2010)

Multi-core parallel simulation of System-level Description Languages. - Rainer Dömer; Weiwei Chen 001; Xu Han 002; Andreas Gerstlauer (ASP-DAC, 2011)

Multicore Simulation of Transaction-Level Models Using the SoC Environment. - Weiwei Chen 001; Xu Han 002; Rainer Dömer (IEEE Des. Test Comput., 2011)

Parallel discrete event simulation of Transaction Level Models. - Rainer Dömer; Weiwei Chen 001; Xu Han 002 (ASP-DAC, 2012)

Out-of-order parallel simulation for ESL design. - Weiwei Chen 001; Xu Han 002; Rainer Dömer (DATE, 2012)

Eliminating race conditions in system-level models by using parallel simulation infrastructure. - Weiwei Chen 001; Che-Wei Chang; Xu Han 002; Rainer Dömer (HLDVT, 2012)

Designer-in-the-loop recoding of ESL models using static parallel access conflict analysis. - Xu Han 002; Weiwei Chen 001; Rainer Dömer (M-SCOPES, 2013)

Advances in Parallel Discrete Event Simulation for Electronic System-Level Design. - Weiwei Chen 001; Xu Han 002; Che-Wei Chang; Rainer Dömer (IEEE Des. Test, 2013)

May-happen-in-parallel analysis based on segment graphs for safe ESL models. - Weiwei Chen 001; Xu Han 002; Rainer Dömer (DATE, 2014)

Out-of-Order Parallel Discrete Event Simulation for Transaction Level Models. - Weiwei Chen 001; Xu Han 002; Che-Wei Chang; Guantao Liu; Rainer Dömer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)