Relating Data Independent Trace Checks in CSP with UNITY Reachability under a Normality Assumption. - Xu Wang 001; A. W. Roscoe 001; Ranko Lazic 001 (IFM, 2004)

Towards a Unifying CSP approach to Hierarchical Verification of Asynchronous Hardware. - Xu Wang 001; Marta Z. Kwiatkowska; Georgios Theodoropoulos 001; Qianyi Zhang (AVoCS, 2004)

Opportunities and Challenges in Process-algebraic Verification of Asynchronous Circuit Designs. - Xu Wang 001; Marta Z. Kwiatkowska; Georgios Theodoropoulos 001; Qianyi Zhang (FMGALS@MEMOCODE, 2005)

Compositional State Space Reduction Using Untangled Actions. - Xu Wang 001; Marta Z. Kwiatkowska (EXPRESS, 2006)

On Process-algebraic Verification of Asynchronous Circuits. - Xu Wang 001; Marta Z. Kwiatkowska (Fundam. Informaticae, 2007)

Towards a Pomset Semantics for a Shared-Variable Parallel Language. - Yongxin Zhao; Xu Wang 001; Huibiao Zhu (UTP, 2010)

Compositional Analysis for Weak Stubborn Sets. - Henri Hansen; Xu Wang 001 (ACSD, 2011)

On the Origin of Events: Branching Cells as Stubborn Sets. - Henri Hansen; Xu Wang 001 (Petri Nets, 2011)

Maximal Confluent Processes. - Xu Wang 001 (Petri Nets, 2012)

Revisiting Timed Specification Theories: A Linear-Time Perspective. - Chris Chilton; Marta Z. Kwiatkowska; Xu Wang 001 (FORMATS, 2012)

Revisiting Timed Specification Theory II : Realisability - Chris Chilton; Marta Z. Kwiatkowska; Xu Wang 001 (CoRR, 2013)

Practical Partial Order Reduction for CSP. - Thomas Gibson-Robinson; Henri Hansen; A. W. Roscoe 001; Xu Wang 001 (NFM, 2015)

OnTrack: The Railway Verification Toolset - Extended Abstract. - Phillip James; Faron Moller; Hoang Nga Nguyen; Markus Roggenbach; Helen Treharne; Xu Wang 001 (ISoLA (2), 2016)

A Specification Theory of Real-Time Processes. - Chris Chilton; Marta Z. Kwiatkowska; Faron Moller; Xu Wang 001 (Concurrency, Security, and Puzzles, 2017)

A simple proof of data-race freedom and coherence for simpson's 4-slot algorithm. - Xu Wang 001; Qiwen Xu (SAC, 2022)