Xu Xu

Affiliations:
  • Synopsys Inc, Mountain View, CA, USA
  • University of California at San Diego, LaJolla, CA, USA (former)


According to our database1, Xu Xu authored at least 20 papers between 2003 and 2010.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2010
Layout Decomposition Approaches for Double Patterning Lithography.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2008
Fast Dual-Graph-Based Hotspot Filtering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Layout decomposition for double patterning lithography.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

2007
Enhanced Design Flow and Optimizations for Multiproject Wafers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Statistical Timing Analysis in the Presence of Signal-Integrity Effects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Fast and Efficient Bright-Field AAPSM Conflict Detection and Correction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Computer-Aided Optimization of DNA Array Design and Manufacturing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Wafer Topography-Aware Optical Proximity Correction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Statistical crosstalk aggressor alignment aware interconnect delay calculation.
Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006

Constructing Current-Based Gate Models Based on Existing Timing Library.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Statistical gate delay calculation with crosstalk alignment consideration.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

2005
Fast and efficient phase conflict detection and correction in standard-cell layouts.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Bright-Field AAPSM Conflict Detection and Correction.
Proceedings of the 2005 Design, 2005

2004
Local unidirectional bias for cutsize-delay tradeoff in performance-driven bipartitioning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Multi-project reticle floorplanning and wafer dicing.
Proceedings of the 2004 International Symposium on Physical Design, 2004

2003
Accurate pseudo-constructive wirelength and congestion estimation.
Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003

Local unidirectional bias for smooth cutsize-delay tradeoff in performance-driven bipartitioning.
Proceedings of the 2003 International Symposium on Physical Design, 2003

Design Flow Enhancements for DNA Arrays.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Evaluation of Placement Techniques for DNA Probe Array Layout.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003


  Loading...