A routability constrained scan chain ordering technique for test power reduction. - Xuan-Lun Huang; Jiun-Lang Huang (ASP-DAC, 2006)

Diagnosing integrator leakage of single-bit first-order DeltaSigma modulator using DC input. - Xuan-Lun Huang; Chen-Yuan Yang; Jiun-Lang Huang (ASP-DAC, 2009)

An On-Chip Integrator Leakage Characterization Technique and Its Application to Switched Capacitor Circuits Testing. - Chen-Yuan Yang; Xuan-Lun Huang; Jiun-Lang Huang (Asian Test Symposium, 2009)

A robust ADC code hit counting technique. - Jiun-Lang Huang; Kuo-Yu Chou; Ming-Huan Lu; Xuan-Lun Huang (DATE, 2010)

An ADC/DAC loopback testing methodology by DAC output offsetting and scaling. - Xuan-Lun Huang; Jiun-Lang Huang (VTS, 2010)

A self-testing and calibration method for embedded successive approximation register ADC. - Xuan-Lun Huang; Ping-Ying Kang; Hsiu-Ming Chang 001; Jiun-Lang Huang; Yung-Fa Chou; Yung-Pin Lee; Ding-Ming Kwai; Cheng-Wen Wu (ASP-DAC, 2011)

A Pre- and Post-bond Self-Testing and Calibration Methodology for SAR ADC Array in 3-D CMOS Imager. - Xuan-Lun Huang; Ping-Ying Kang; Jiun-Lang Huang; Yung-Fa Chou; Yung-Pin Lee; Ding-Ming Kwai (ETS, 2011)

Histogram-Based Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADCs. - Xuan-Lun Huang; Ping-Ying Kang; Yuan-Chi Yu; Jiun-Lang Huang (J. Electron. Test., 2011)

ADC/DAC Loopback Linearity Testing by DAC Output Offsetting and Scaling. - Xuan-Lun Huang; Jiun-Lang Huang (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A Built-In Characterization Technique for 1-Bit/Stage Pipelined ADC. - Y.-H. Chou; Jiun-Lang Huang; Xuan-Lun Huang (Asian Test Symposium, 2012)

An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration. - Xuan-Lun Huang; Jiun-Lang Huang; Hung-I Chen; Chang-Yu Chen; Tseng Kuo-Tsai; Ming-Feng Huang; Yung-Fa Chou; Ding-Ming Kwai (J. Electron. Test., 2012)

A mutual characterization based SAR ADC self-testing technique. - H.-J. Lin; Xuan-Lun Huang; Jiun-Lang Huang (ETS, 2013)

An IDDQ-based source driver IC design-for-test technique. - S.-S. Lin; C.-L. Kao; Jiun-Lang Huang; C.-C. Lee; Xuan-Lun Huang (ICCAD, 2013)

A 58.9-dB ACR, 85.5-dB SBA, 5-26-MHz Configurable-Bandwidth, Charge-Domain Filter in 65-nm CMOS. - Ming-Feng Huang; Ming-Ching Kuo; Tzu-Yi Yang; Xuan-Lun Huang (IEEE J. Solid State Circuits, 2013)

FPGA-Based Subset Sum Delay Lines. - Chung-Yun Wang; Yu-Yi Chen; Jiun-Lang Huang; Xuan-Lun Huang (ATS, 2014)

Design and Implementation of an FPGA-Based Data/Timing Formatter. - Yu-Yi Chen; Jiun-Lang Huang; Terry Kuo; Xuan-Lun Huang (J. Electron. Test., 2015)

A Scalable Photonic Computer Solving the Subset Sum Problem. - Xiao Yun Xu; Xuan-Lun Huang; Zhan-Ming Li; Jun Gao; Zhi-Qiang Jiao; Yao Wang; Ruo-Jing Ren; H. P. Zhang; Xian-Min Jin (CoRR, 2020)