Design-for-Test of Asynchronous Networks-on-Chip. - Xuan-Tu Tran; Vincent Beroulle; Jean Durupt; Chantal Robach; François Bertrand (DDECS, 2006)

A DFT Architecture for Asynchronous Networks-on-Chip. - Xuan-Tu Tran; Jean Durupt; François Bertrand; Vincent Beroulle; Chantal Robach (ETS, 2006)

Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip. - Xuan-Tu Tran; Jean Durupt; Yvain Thonnart; François Bertrand; Vincent Beroulle; Chantal Robach (NOCS, 2007)

A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application. - Xuan-Tu Tran; Yvain Thonnart; Jean Durupt; Vincent Beroulle; Chantal Robach (NOCS, 2008)

Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application. - Xuan-Tu Tran; Yvain Thonnart; Jean Durupt; Vincent Beroulle; Chantal Robach (IET Comput. Digit. Tech., 2009)

An Asynchronous Power Aware and Adaptive NoC Based Circuit. - Edith Beigné; Fabien Clermidy; Hélène Lhermet; Sylvain Miermont; Yvain Thonnart; Xuan-Tu Tran; Alexandre Valentian; Didier Varreau; Pascal Vivet; Xavier Popon; Hugo Lebreton (IEEE J. Solid State Circuits, 2009)

User Interest Analysis with Hidden Topic in News Recommendation System. - Mai-Vu Tran; Xuan-Tu Tran; Huy-Long Uong (IALP, 2010)

Cost-efficient 130nm TSMC Forward Transform and Quantization for H.264/AVC encoders. - Xuan-Tu Tran; Van-Huan Tran (DDECS, 2011)

A Model of Vietnamese Person Named Entity Question Answering System. - Mai-Vu Tran; Duc-Trong Le; Xuan-Tu Tran; Tien-Tung Nguyen (PACLIC, 2012)

Design and Implementation of a SoPC System for Speech Recognition. - Tran Van Hoang; Thien Truong Nguyen-Ly; Hoang Trang; Xuan-Tu Tran (MUE, 2013)

High-performance adaption of ARM processors into Network-on-Chip architectures. - Tung Nguyen; Duy-Hieu Bui; Hai-Phong Phan; Trong-Trinh Dang; Xuan-Tu Tran (SoCC, 2013)

A generalized model for investigating scheduling schemes in computational clusters. - Tien Van Do 001; Binh Thai Vu; Xuan-Tu Tran; Anh P. Nguyen (Simul. Model. Pract. Theory, 2013)

H.264/AVC hardware encoders and low-power features. - Ngoc-Mai Nguyen; Edith Beigné; Suzanne Lesecq; Duy-Hieu Bui; Nam-Khanh Dang; Xuan-Tu Tran (APCCAS, 2014)

Reducing temporal redundancy in MJPEG using Zipfian estimation techniques. - Ngoc-Sinh Nguyen; Duy-Hieu Bui; Xuan-Tu Tran (APCCAS, 2014)

An efficient hardware architecture for inter-prediction in H.264/AVC encoders. - Nam-Khanh Dang; Xuan-Tu Tran; Alain Merirot (DDECS, 2014)

FIFO-level-based power management and its application to an H.264 encoder. - Ngoc-Mai Nguyen; Warody Lombardi; Edith Beigné; Suzanne Lesecq; Xuan-Tu Tran (IECON, 2014)

Soft-error resilient 3D Network-on-Chip router. - Khanh N. Dang; Michael Conrad Meyer; Yuichi Okuyama 001; Abderazek Ben Abdallah; Xuan-Tu Tran (iCAST, 2015)

Ultra low-power and low-energy 32-bit datapath AES architecture for IoT applications. - Duy-Hieu Bui; Diego Puschini; Simone Bacles-Min; Edith Beigné; Xuan-Tu Tran (ICICDT, 2016)

Power consumption estimation using VNOC2.0 simulator for a fuzzy-logic based low power Network-on-Chip. - Hai-Phong Phan; Xuan-Tu Tran; Tomohiro Yoneda (ICICDT, 2017)

AXI-NoC: High-Performance Adaptation Unit for ARM Processors in Network-on-Chip Architectures. - Xuan-Tu Tran; Tung Nguyen; Hai-Phong Phan; Duy-Hieu Bui (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

AES Datapath Optimization Strategies for Low-Power Low-Energy Multisecurity-Level Internet-of-Things Applications. - Duy-Hieu Bui; Diego Puschini; Simone Bacles-Min; Edith Beigné; Xuan-Tu Tran (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model. - Khanh N. Dang; Akram Ben Ahmed; Xuan-Tu Tran; Yuichi Okuyama 001; Abderazek Ben Abdallah (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A novel priority-driven arbiter for the router in reconfigurable Network-on-Chips. - Hung K. Nguyen; Xuan-Tu Tran (ICICDT, 2018)

Parity-Based ECC and Mechanism for Detecting and Correcting Soft Errors in On-Chip Communication. - Khanh N. Dang; Xuan-Tu Tran (MCSoC, 2018)

2D-PPC: A single-correction multiple-detection method for Through-Silicon-Via Faults. - Khanh N. Dang; Michael Conrad Meyer; Akram Ben Ahmed; Abderazek Ben Abdallah; Xuan-Tu Tran (APCCAS, 2019)

A Novel Hardware Architecture for Human Detection using HOG-SVM Co-Optimization. - Ngo-Doanh Nguyen; Duy-Hieu Bui; Xuan-Tu Tran (APCCAS, 2019)

A Wideband High Efficiency Ka-Band MMIC Power Amplifier for 5G Wireless Communications. - Duy P. Nguyen; Xuan-Tu Tran; Nguyen L. K. Nguyen; Phat T. Nguyen; Anh-Vu Pham (ISCAS, 2019)

A 45nm High-Throughput and Low Latency AES Encryption for Real-Time Applications. - Pham-Khoi Dong; Hung K. Nguyen; Xuan-Tu Tran (ISCIT, 2019)

TSV-IaS: Analytic Analysis and Low-Cost Non-Preemptive on-Line Detection and Correction Method for TSV Defects. - Khanh N. Dang; Akram Ben Ahmed; Abderazek Ben Abdallah; Xuan-Tu Tran (ISVLSI, 2019)

An on-Communication Multiple-TSV Defects Detection and Localization for Real-Time 3D-ICs. - Khanh N. Dang; Akram Ben Ahmed; Xuan-Tu Tran (MCSoC, 2019)

High Gain High Efficiency Doherty Amplifiers with Optimized Driver Stages. - Duy P. Nguyen; Xuan-Tu Tran; Phat T. Nguyen; Nguyen L. K. Nguyen; Anh-Vu Pham (MWSCAS, 2019)

An Efficient Event-driven Neuromorphic Architecture for Deep Spiking Neural Networks. - Duy-Anh Nguyen; Duy-Hieu Bui; Francesca Iacopi; Xuan-Tu Tran (SoCC, 2019)

A novel reconfigurable router for QoS guarantees in real-time NoC-based MPSoCs. - Hung K. Nguyen; Xuan-Tu Tran (J. Syst. Archit., 2019)

Low-Power Implementation of a High-Throughput Multi-core AES Encryption Architecture. - Pham-Khoi Dong; Hung K. Nguyen; Van-Phuc Hoang; Xuan-Tu Tran (APCCAS, 2020)

A Lightweight AEAD encryption core to secure IoT applications. - Ngo-Doanh Nguyen; Duy-Hieu Bui; Xuan-Tu Tran (APCCAS, 2020)

A lightweight Max-Pooling method and architecture for Deep Spiking Convolutional Neural Networks. - Duy-Anh Nguyen; Xuan-Tu Tran; Khanh N. Dang; Francesca Iacopi (APCCAS, 2020)

FPGA-Based Lightweight Hardware Architecture of the PHOTON Hash Function for IoT Edge Devices. - Mohammed Omar Awadh Al-Shatari; Fawnizu Azmadi Hussin; Azrina Abd Aziz; Gunawan Witjaksono; Xuan-Tu Tran (IEEE Access, 2020)

A Thermal-Aware On-Line Fault Tolerance Method for TSV Lifetime Reliability in 3D-NoC Systems. - Khanh N. Dang; Akram Ben Ahmed; Abderazek Ben Abdallah; Xuan-Tu Tran (IEEE Access, 2020)

A Non-Blocking Non-Degrading Multiple Defects Link Testing Method for 3D-Networks-on-Chip. - Khanh N. Dang; Michael Conrad Meyer; Akram Ben Ahmed; Abderazek Ben Abdallah; Xuan-Tu Tran (IEEE Access, 2020)

Report on power, thermal and reliability prediction for 3D Networks-on-Chip. - Khanh N. Dang; Akram Ben Ahmed; Abderazek Ben Abdallah; Xuan-Tu Tran (CoRR, 2020)

Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB). - Trong-Thuc Hoang; Ckristian Duran; Khai-Duy Nguyen; Tuan-Kiet Dang; Quynh Nguyen Quang Nhu; Phuc Hong Than; Xuan-Tu Tran; Duc-Hung Le; Akira Tsukamoto; Kuniyasu Suzaki; Cong-Kha Pham (IEICE Electron. Express, 2020)

Reducing Bitrate and Increasing the Quality of Inter Frame by Avoiding Quantization Errors in Stationary Blocks. - Xuan-Tu Tran; Ngoc-Sinh Nguyen; Duy-Hieu Bui; Minh-Trien Pham; Hung K. Nguyen; Cong-Kha Pham (EAI Endorsed Trans. Ind. Networks Intell. Syst., 2020)

TSV-OCT: A Scalable Online Multiple-TSV Defects Localization for Real-Time 3-D-IC Systems. - Khanh N. Dang; Akram Ben Ahmed; Abderazek Ben Abdallah; Xuan-Tu Tran (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A proposal for enhancing training speed in deep learning models based on memory activity survey. - Tuan-Kiet Dang; Binh Kieu-Do-Nguyen; Trong-Thuc Hoang; Khai-Duy Nguyen; Xuan-Tu Tran; Cong-Kha Pham (IEICE Electron. Express, 2021)

A trigonometric hardware acceleration in 32-bit RISC-V microcontroller with custom instruction. - Khai-Duy Nguyen; Tuan-Kiet Dang; Trong-Thuc Hoang; Quynh Nguyen Quang Nhu; Xuan-Tu Tran; Cong-Kha Pham (IEICE Electron. Express, 2021)

A Sub-μ W Reversed-Body-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box (SOTB) for IoT Applications. - Marco Sarmiento; Khai-Duy Nguyen; Ckristian Duran; Trong-Thuc Hoang; Ronaldo Serrano; Van-Phuc Hoang; Xuan-Tu Tran; Koichiro Ishibashi; Cong-Kha Pham (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

An Adaptive Hardware Architecture using Quantized HOG Features for Object Detection. - Ngo-Doanh Nguyen; Duy-Hieu Bui; Fawnizu Azmadi Hussin; Xuan-Tu Tran (ICICDT, 2022)

GAQ-SNN: A Genetic Algorithm based Quantization Framework for Deep Spiking Neural Networks. - Duy-Anh Nguyen; Xuan-Tu Tran; Francesca Iacopi (ICICDT, 2022)

Composite Lightweight Authenticated Encryption Based on LED Block Cipher and PHOTON Hash Function for IoT Devices. - Mohammed Omar Awadh Al-Shatari; Fawnizu Azmadi Hussin; Azrina Abd Aziz; Mohd Saufy Rohmad; Xuan-Tu Tran (MCSoC, 2022)

HotCluster: A Thermal-Aware Defect Recovery Method for Through-Silicon-Vias Toward Reliable 3-D ICs Systems. - Khanh N. Dang; Akram Ben Ahmed; Abderazek Ben Abdallah; Xuan-Tu Tran (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Design and Implementation of a Coarse-grained Dynamically Reconfigurable Multimedia Accelerator. - Hung K. Nguyen; Xuan-Tu Tran (ACM Trans. Parallel Comput., 2022)

A low-power, high-accuracy with fully on-chip ternary weight hardware architecture for Deep Spiking Neural Networks. - Duy-Anh Nguyen; Xuan-Tu Tran; Khanh N. Dang; Francesca Iacopi (Microprocess. Microsystems, 2022)

Low-cost Low-Power Implementation of Binary Edwards Curve for Secure Passive RFID Tags. - Hiep Manh Dao; Vincent Beroulle; Yann Kieffer; Xuan-Tu Tran; Duy-Hieu Bui (MCSoC, 2023)

An In-Situ Dynamic Quantization With 3D Stacking Synaptic Memory for Power-Aware Neuromorphic Architecture. - Ngo-Doanh Nguyen; Xuan-Tu Tran; Abderazek Ben Abdallah; Khanh N. Dang (IEEE Access, 2023)

A light-weight neuromorphic controlling clock gating based multi-core cryptography platform. - Pham-Khoi Dong; Khanh N. Dang; Duy-Anh Nguyen; Xuan-Tu Tran (Microprocess. Microsystems, 2024)