WinoNN: optimising FPGA-based neural network accelerators using fast winograd algorithm (work-in-progress). - Xuan Wang 020; Chao Wang 003; Xuehai Zhou (CODES+ISSS, 2018)

WinoNN: Optimizing FPGA-Based Convolutional Neural Network Accelerators Using Sparse Winograd Algorithm. - Xuan Wang 020; Chao Wang 003; Jing Cao; Lei Gong; Xuehai Zhou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

UH-JLS: A Parallel Ultra-High Throughput JPEG-LS Encoding Architecture for Lossless Image Compression. - Xuan Wang 020; Lei Gong; Chao Wang 003; Xi Li 003; Xuehai Zhou (ICCD, 2021)

NAF: Deeper Network/Accelerator Co-Exploration for Customizing CNNs on FPGA. - Wenqi Lou; Jiaming Qian; Lei Gong; Xuan Wang 020; Chao Wang 003; Xuehai Zhou (DATE, 2023)

hAP: A Spatial-von Neumann Heterogeneous Automata Processor with Optimized Resource and IO Overhead on FPGA. - Xuan Wang 020; Lei Gong; Jing Cao; Wenqi Lou; Weiya Wang; Chao Wang 003; Xuehai Zhou (FPGA, 2023)

Unleashing Network/Accelerator Co-Exploration Potential on FPGAs: A Deeper Joint Search. - Wenqi Lou; Lei Gong; Chao Wang 003; Jiaming Qian; Xuan Wang 020; Changlong Li; Xuehai Zhou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

FlexBCM: Hybrid Block-Circulant Neural Network and Accelerator Co-Search on FPGAs. - Wenqi Lou; Yunji Qin; Xuan Wang 020; Lei Gong; Chao Wang 003; Xuehai Zhou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)