Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches. - Pei-Yuan Chou; I-Chen Wu; Jai-Wei Lin; Xuan-Yu Lin; Tien-Fu Chen; Tay-Jyi Lin; Jinn-Shyan Wang (ASICON, 2015)

ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures. - Po-Hao Wang; Yung-Chen Chien; Shang-Jen Tsai; Xuan-Yu Lin; Rizal Tanjung; Yi-Sian Lin; Shu-Wei Syu; Tay-Jyi Lin; Jinn-Shyan Wang; Tien-Fu Chen (IEEE Trans. Very Large Scale Integr. Syst., 2017)