A constraint-based placement refinement method for CMOS analog cell layout. - Xuan Zeng 001; J. Guan; Wenqing Zhao; Pushan Tang; Dian Zhou (ISCAS (6), 1999)

Buffer insertion for clock delay and skew minimization. - Xuan Zeng 001; Dian Zhou; Wei Li (ISPD, 1999)

Parasitic and mismatch modeling for optimal stack generation [in CMOS]. - Xuan Zeng 001; Mingyuan Li; Wenqing Zhao; Pushan Tang; Dian Zhou (ISCAS, 2000)

Behavioral Modeling of Analog Circuits by Wavelet Collocation Method. - Xin Li 001; Xuan Zeng 001; Dian Zhou; Xieting Ling (ICCAD, 2001)

A wavelet balance approach for steady-state analysis of nonlinear circuits. - Xin Li 001; Bo Hu 002; Xieting Ling; Xuan Zeng 001 (ISCAS (3), 2001)

Automatic clock tree design with IPs in the system. - Wei Li; Dian Zhou; Haksu Kim; Xuan Zeng 001 (ISCAS (5), 2001)

Wavelet method for high-speed clock tree simulation. - Xin Li 001; Xuan Zeng 001; Dian Zhou; Xieting Ling (ISCAS (1), 2002)

Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing. - Ruiming Li; Dian Zhou; Jin Liu 004; Xuan Zeng 001 (ICCAD, 2003)

An efficient Sylvester equation solver for time domain circuit simulation by wavelet collocation method. - Xuan Zeng 001; Sheng Huang; Yangfeng Su; Dian Zhou (ISCAS (4), 2003)

An error distribution based nonlinear companding method for analog behavioral modeling via wavelet approximation. - Xuan Zeng 001; Jun Tao 001; Yangfeng Su; Wenbing Chen; Dian Zhou (ISCAS (3), 2003)

Behavioral modeling for analog system-level simulation by wavelet collocation method. - Xin Li 001; Xuan Zeng 001; Dian Zhou; Xieting Ling; Wei Cai 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2003)

Analog circuit behavioral modeling via wavelet collocation method with auto-companding. - Jian Wang; Jun Tao 001; Xuan Zeng 001; Charles C. Chiang; Dian Zhou (ASP-DAC, 2004)

Direct Nonlinear Order Reduction with Variational Analysis. - Lihong Feng; Xuan Zeng 001; Charles C. Chiang; Dian Zhou; Qiang Fang (DATE, 2004)

Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method. - Xin Zhou; Dian Zhou; Jin Liu 004; Ruiming Li; Xuan Zeng 001; Charles C. Chiang (DATE, 2004)

SAPOR: second-order Arnoldi method for passive order reduction of RCS circuits. - Yangfeng Su; Jian Wang; Xuan Zeng 001; Zhaojun Bai; Charles C. Chiang; Dian Zhou (ICCAD, 2004)

Two-sided projection method in variational equation model order reduction of nonlinear circuits. - Lihong Feng; Xuan Zeng 001; Jiarong Tong; Charles C. Chiang; Dian Zhou (ISCAS (4), 2004)

Frequency domain wavelet method with GMRES for large-scale linear circuit simulation. - Jian Wang; Xuan Zeng 001; Wei Cai 003; Charles C. Chiang; Jiarong Tong; Dian Zhou (ISCAS (5), 2004)

Block SAPOR: block Second-order Arnoldi method for Passive Order Reduction of multi-input multi-output RCS interconnect circuits. - Bang Liu; Xuan Zeng 001; Yangfeng Su; Jun Tao 001; Zhaojun Bai; Charles C. Chiang; Dian Zhou (ASP-DAC, 2005)

A novel wavelet method for noise analysis of nonlinear circuits. - Xuan Zeng 001; Bang Liu; Jun Tao 001; Charles C. Chiang; Dian Zhou (ASP-DAC, 2005)

Power-optimal simultaneous buffer insertion/sizing and uniform wire sizing for single long wires. - Ruiming Li; Dian Zhou; Jin Liu 004; Xuan Zeng 001 (ISCAS (1), 2005)

Power-optimal simultaneous buffer insertion/sizing and wire sizing for two-pin nets. - Ruiming Li; Dian Zhou; Jin Liu 004; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

A Spectral Stochastic Collocation Method for Capacitance Extraction of Interconnects with Process Variations. - Hengliang Zhu; Xuan Zeng 001; Wei Cai 003; Dian Zhou (APCCAS, 2006)

Time domain model order reduction by wavelet collocation method. - Xuan Zeng 001; Lihong Feng; Yangfeng Su; Wei Cai 003; Dian Zhou; Charles C. Chiang (DATE, 2006)

A one-shot projection method for interconnects with process variations. - Jun Tao 001; Xuan Zeng 001; Fan Yang 001; Yangfeng Su; Lihong Feng; Wei Cai 003; Dian Zhou; Charles C. Chiang (ISCAS, 2006)

Robust Analog Circuit Sizing Using Ellipsoid Method and Affine Arithmetic. - Xuexin Liu; Wai-Shing Luk; Yu Song; Pushan Tang; Xuan Zeng 001 (ASP-DAC, 2007)

Stochastic Sparse-grid Collocation Algorithm (SSCA) for Periodic Steady-State Analysis of Nonlinear System with Process Variations. - Jun Tao 001; Xuan Zeng 001; Wei Cai 003; Yangfeng Su; Dian Zhou; Charles C. Chiang (ASP-DAC, 2007)

WCOMP: Waveform Comparison Tool for Mixed-signal Validation Regression in Memory Design. - Peng Zhang; Wai-Shing Luk; Yu Song; Jiarong Tong; Pushan Tang; Xuan Zeng 001 (ASP-DAC, 2007)

A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology. - Hengliang Zhu; Xuan Zeng 001; Wei Cai 003; Jintao Xue; Dian Zhou (DATE, 2007)

Parameterized model order reduction via a two-directional Arnoldi process. - Yung-Ta Li; Zhaojun Bai; Yangfeng Su; Xuan Zeng 001 (ICCAD, 2007)

RLCSYN: RLC Equivalent Circuit Synthesis for Structure-Preserved Reduced-order Model of Interconnect. - Fan Yang 001; Xuan Zeng 001; Yangfeng Su; Dian Zhou (ISCAS, 2007)

A Novel Optimization Method for Parametric Yield: Uniform Design Mapping Distance Algorithm. - Ming-e Jing; Yue Hao; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays. - Yi Wang; Wai-Shing Luk; Xuan Zeng 001; Jun Tao 001; Changhao Yan; Jiarong Tong; Wei Cai 003; Jia Ni (DAC, 2008)

Characterizing Intra-Die Spatial Correlation Using Spectral Density Method. - Qiang Fu; Wai-Shing Luk; Jun Tao 001; Changhao Yan; Xuan Zeng 001 (ISQED, 2008)

Adaptive Stochastic Collocation Method (ASCM) for Parameterized Statistical Timing Analysis with Quadratic Delay Model. - Yi Wang; Xuan Zeng 001; Jun Tao 001; Hengliang Zhu; Xu Luo; Changhao Yan; Wei Cai 003 (ISQED, 2008)

Adaptive Stochastic Collocation Method for Parameterized Statistical Timing Analysis with Quadratic Delay Model. - Yi Wang; Xuan Zeng 001; Jun Tao 001; Hengliang Zhu; Wei Cai 003 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Model Order Reduction of Parameterized Interconnect Networks via a Two-Directional Arnoldi Process. - Yung-Ta Li; Zhaojun Bai; Yangfeng Su; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Statistical analysis of on-chip power grid networks by variational extended truncated balanced realization method. - Duo Li; Sheldon X.-D. Tan; Gengsheng Chen; Xuan Zeng 001 (ASP-DAC, 2009)

Provably good and practically efficient algorithms for CMP dummy fill. - Chunyang Feng; Hai Zhou 001; Changhao Yan; Jun Tao 001; Xuan Zeng 001 (DAC, 2009)

Statistical reliability analysis under process variation and aging effects. - Yinghai Lu; Li Shang; Hai Zhou 001; Hengliang Zhu; Fan Yang 001; Xuan Zeng 001 (DAC, 2009)

Multicore parallel min-cost flow algorithm for CAD applications. - Yinghai Lu; Hai Zhou 001; Li Shang; Xuan Zeng 001 (DAC, 2009)

Binning optimization based on SSTA for transparently-latched circuits. - Min Gong; Hai Zhou 001; Jun Tao 001; Xuan Zeng 001 (ICCAD, 2009)

Incremental Circuit Simulation Analysis for Design Modification and Verification. - Tracey Y. Zhou; Dian Zhou; Xuan Zeng 001 (ISCAS, 2009)

Characterizing Intra-Die Spatial Correlation Using Spectral Density Fitting Method. - Qiang Fu; Wai-Shing Luk; Jun Tao 001; Changhao Yan; Xuan Zeng 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Intra-Die Spatial Correlation Extraction with Maximum Likelihood Estimation Method for Multiple Test Chips. - Qiang Fu; Wai-Shing Luk; Jun Tao 001; Xuan Zeng 001; Wei Cai 003 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

A Modified Nested Sparse Grid Based Adaptive Stochastic Collocation Method for Statistical Static Timing Analysis. - Xu Luo; Fan Yang 001; Xuan Zeng 001; Jun Tao 001; Hengliang Zhu; Wei Cai 003 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Generalized Stochastic Collocation Method for Variation-Aware Capacitance Extraction of Interconnects Considering Arbitrary Random Probability. - Hengliang Zhu; Xuan Zeng 001; Xu Luo; Wei Cai 003 (IEICE Trans. Electron., 2009)

Global routing and track assignment for flip-chip designs. - Xiaodong Liu 018; Yifan Zhang; Gary K. Yeap; Chunlei Chu; Jian Sun 005; Xuan Zeng 001 (DAC, 2010)

An efficient transistor-level piecewise-linear macromodeling approach for model order reduction of nonlinear circuits. - Xiaoda Pan; Fan Yang 001; Xuan Zeng 001; Yangfeng Su (DATE, 2010)

Intel LVS logic as a combinational logic paradigm in CNT technology. - Bao Liu; Zhen Cao; Jun Tao 001; Xuan Zeng 001; Pushan Tang; H.-S. Philip Wong (NANOARCH, 2010)

Stochastic Sparse-Grid Collocation Algorithm for Steady-State Analysis of Nonlinear System with Process Variations. - Jun Tao 001; Xuan Zeng 001; Wei Cai 003; Yangfeng Su; Dian Zhou (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

NHAR: A non-homogeneous Arnoldi method for fast simulation of RCL circuits with a large number of ports. - Xuan Zeng 001; Fan Yang 001; Yangfeng Su; Wei Cai 003 (Int. J. Circuit Theory Appl., 2010)

Multicore Parallelization of Min-Cost Flow for CAD Applications. - Yinghai Lu; Hai Zhou 001; Li Shang; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

A Wavelet-Collocation-Based Trajectory Piecewise-Linear Algorithm for Time-Domain Model-Order Reduction of Nonlinear Circuits. - Ke Zong; Fan Yang 001; Xuan Zeng 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Low power discrete voltage assignment under clock skew scheduling. - Li Li 021; Jian Sun 005; Yinghai Lu; Hai Zhou 001; Xuan Zeng 001 (ASP-DAC, 2011)

Post-routing layer assignment for double patterning. - Jian Sun 005; Yinghai Lu; Hai Zhou 001; Xuan Zeng 001 (ASP-DAC, 2011)

Parallel cross-layer optimization of high-level synthesis and physical design. - James Williamson; Yinghai Lu; Li Shang; Hai Zhou 001; Xuan Zeng 001 (ASP-DAC, 2011)

A practical method for multi-domain clock skew optimization. - Yanling Zhi; Hai Zhou 001; Xuan Zeng 001 (ASP-DAC, 2011)

An integrated algorithm for 3D-IC TSV assignment. - Xiaodong Liu 018; Yifan Zhang; Gary K. Yeap; Xuan Zeng 001 (DAC, 2011)

An efficient algorithm for multi-domain clock skew scheduling. - Yanling Zhi; Wai-Shing Luk; Hai Zhou 001; Changhao Yan; Hengliang Zhu; Xuan Zeng 001 (DATE, 2011)

A new method for multiparameter robust stability distribution analysis of linear analog circuits. - Changhao Yan; Sheng-Guo Wang; Xuan Zeng 001 (ICCAD, 2011)

Stochastic Non-homogeneous Arnoldi Method for Analysis of On-Chip Power Grid Networks under Process Variations. - Zhihua Gui; Fan Yang 001; Xuan Zeng 001 (IEICE Trans. Electron., 2011)

Efficient Approximation Algorithms for Chemical Mechanical Polishing Dummy Fill. - Chunyang Feng; Hai Zhou 001; Changhao Yan; Jun Tao 001; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Binning Optimization for Transparently-Latched Circuits. - Min Gong; Hai Zhou 001; Li Li 021; Jun Tao 001; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Full-Spectrum Spatial-Temporal Dynamic Thermal Analysis for Nanometer-Scale Integrated Circuits. - Zyad Hassan; Nicholas Allec; Fan Yang 001; Li Shang; Robert P. Dick; Xuan Zeng 001 (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Improved tangent space based distance metric for accurate lithographic hotspot classification. - Jing Guo; Fan Yang 001; Subarna Sinha; Charles C. Chiang; Xuan Zeng 001 (DAC, 2012)

AMOR: an efficient aggregating based model order reduction method for many-terminal interconnect circuits. - Yangfeng Su; Fan Yang 001; Xuan Zeng 001 (DAC, 2012)

Yield-Driven Clock Skew Scheduling for Arbitrary Distributions of Critical Path Delays. - Yanling Zhi; Wai-Shing Luk; Yi Wang; Changhao Yan; Xuan Zeng 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Mixed-signal system verification by SystemC/SystemC-AMS and HSIM-VCS in near field communication tag design. - Zhaori Bi; Wei Li; Dian Zhou; Xuan Zeng 001; Sheng-Guo Wang (ASICON, 2013)

Graph Steiner tree construction and its routing applications. - Jun Dong; Hengliang Zhu; Min Xie; Xuan Zeng 001 (ASICON, 2013)

A practical method for auto-design and optimization of DC-DC buck converter. - Guanming Huang; Dian Zhou; Xuan Zeng 001; Shengguo Wang (ASICON, 2013)

FMSSQP: An efficient global optimization tool for the robust design of Rail-to-Rail Op-Amp. - Minghua Li; Dian Zhou; Sheng-Guo Wang; Xuan Zeng 001 (ASICON, 2013)

Oscillator phase noise verification accounting for process variations. - Liuxi Qian; Dian Zhou; Xuan Zeng 001; Shengguo Wang (ASICON, 2013)

A parallel sparse linear system solver for large-scale circuit simulation based on Schur Complement. - Liuxi Qian; Dian Zhou; Xuan Zeng 001; Fan Yang 001; Shengguo Wang (ASICON, 2013)

Layout decomposition with pairwise coloring for multiple patterning lithography. - Ye Zhang 011; Wai-Shing Luk; Hai Zhou 001; Changhao Yan; Xuan Zeng 001 (ICCAD, 2013)

Post-routing layer assignment for double patterning with timing critical paths consideration. - Jian Sun 005; Yinghai Lu; Hai Zhou 001; Changhao Yan; Xuan Zeng 001 (Integr., 2013)

An efficient method for gradient-aware dummy fill synthesis. - Peng Wu; Hai Zhou 001; Changhao Yan; Jun Tao 001; Xuan Zeng 001 (Integr., 2013)

SmipRef: An efficient method for multi-domain clock skew scheduling. - Yanling Zhi; Wai-Shing Luk; Hai Zhou 001; Xuan Zeng 001 (Integr., 2013)

A Parallel Method for Solving Laplace Equations with Dirichlet Data Using Local Boundary Integral Equations and Random Walks. - Changhao Yan; Wei Cai 003; Xuan Zeng 001 (SIAM J. Sci. Comput., 2013)

An Efficient Optimization Based Method to Evaluate the DRV of SRAM Cells. - Guanming Huang; Liuxi Qian; Siwat Saibua; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Near-Field Communication Transceiver System Modeling and Analysis Using SystemC/SystemC-AMS With the Consideration of Noise Issues. - Wei Li; Dian Zhou; Minghua Li; Binh P. Nguyen; Xuan Zeng 001 (IEEE Trans. Very Large Scale Integr. Syst., 2013)

BMF-BD: Bayesian Model Fusion on Bernoulli Distribution for Efficient Yield Estimation of Integrated Circuits. - Chenlei Fang; Fan Yang 001; Xuan Zeng 001; Xin Li 001 (DAC, 2014)

Recovery-based resilient latency-insensitive systems. - Yuankai Chen; Xuan Zeng 001; Hai Zhou 001 (DATE, 2014)

Efficient Statistical Timing Analysis for Circuits with Post-Silicon Tunable Buffers. - Xingbao Zhou; Fan Yang 001; Hai Zhou 001; Min Gong; Hengliang Zhu; Ye Zhang 011; Xuan Zeng 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Integrated Algorithm for 3-D IC Through-Silicon Via Assignment. - Xiaodong Liu 018; Gary K. Yeap; Jun Tao 001; Xuan Zeng 001 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

SIPredict: Efficient post-layout waveform prediction via System Identification. - Qicheng Huang; Xiao Li 002; Fan Yang 001; Xuan Zeng 001; Xin Li 001 (ASP-DAC, 2015)

Layout decomposition co-optimization for hybrid e-beam and multiple patterning lithography. - Yunfeng Yang; Wai-Shing Luk; Hai Zhou 001; Changhao Yan; Xuan Zeng 001; Dian Zhou (ASP-DAC, 2015)

Machine learning and pattern matching in physical design. - Bei Yu 001; David Z. Pan; Tetsuaki Matsunawa; Xuan Zeng 001 (ASP-DAC, 2015)

PGMOR: An Efficient Model Order Reduction Method for Power Grids. - Qicheng Huang; Xiao Li 002; Chenlei Fang; Fan Yang 001; Yangfeng Su; Xuan Zeng 001 (CAD/Graphics, 2015)

Efficient multivariate moment estimation via Bayesian model fusion for analog and mixed-signal circuits. - Qicheng Huang; Chenlei Fang; Fan Yang 001; Xuan Zeng 001; Xin Li 001 (DAC, 2015)

Efficient bit error rate estimation for high-speed link by Bayesian model fusion. - Chenlei Fang; Qicheng Huang; Fan Yang 001; Xuan Zeng 001; Xin Li 001; Chenjie Gu (DATE, 2015)

Analog circuit performance bound estimation based on extreme value theory. - Minghua Li; Zhaori Bi; Dian Zhou; Xuan Zeng 001 (MWSCAS, 2015)

Rapid estimation of the probability of SRAM failure via adaptive multi-level sliding-window statistical method. - Zhenyu Wu; Changhao Yan; Xuan Zeng 001; Sheng-Guo Wang (Integr., 2015)

Multi-parameter clock skew scheduling. - Xingbao Zhou; Wai-Shing Luk; Hai Zhou 001; Fan Yang 001; Changhao Yan; Xuan Zeng 001 (Integr., 2015)

MOS Table Models for Fast and Accurate Simulation of Analog and Mixed-Signal Circuits Using Efficient Oscillation-Diminishing Interpolations. - Xiao Li 002; Fan Yang 001; Dake Wu; Zhenya Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Efficient Transient Analysis of Power Delivery Network With Clock/Power Gating by Sparse Approximation. - Hengliang Zhu; Yuanzhe Wang; Frank Liu 001; Xin Li 001; Xuan Zeng 001; Peter Feldmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography. - Ye Zhang 011; Wai-Shing Luk; Yunfeng Yang; Hai Zhou 001; Changhao Yan; David Z. Pan; Xuan Zeng 001 (ACM Trans. Design Autom. Electr. Syst., 2015)

Automated Technology Migration Methodology for Mixed-Signal Circuit Based on Multistart Optimization Framework. - Liuxi Qian; Zhaori Bi; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

An efficient trajectory-based algorithm for model order reduction of nonlinear systems via localized projection and global interpolation. - Chenjie Yang; Fan Yang 001; Xuan Zeng 001; Dian Zhou (ASP-DAC, 2016)

Algorithms in ParAFEMImp: A Parallel and Wideband Impedance Extraction Program for Complicated 3-D Geometries. - Tao Cui; Junqing Chen; Hengliang Zhu; Xuan Zeng 001 (BigDataSecurity/HPSC/IDS, 2016)

Efficient performance modeling of analog integrated circuits via kernel density based sparse regression. - Chenlei Fang; Qicheng Huang; Fan Yang 001; Xuan Zeng 001; Dian Zhou; Xin Li 001 (DAC, 2016)

Efficient performance modeling via Dual-Prior Bayesian Model Fusion for analog and mixed-signal circuits. - Qicheng Huang; Chenlei Fang; Fan Yang 001; Xuan Zeng 001; Dian Zhou; Xin Li 001 (DAC, 2016)

Efficient spatial variation modeling via robust dictionary learning. - Changhai Liao; Jun Tao 001; Xuan Zeng 001; Yangfeng Su; Dian Zhou; Xin Li 001 (DATE, 2016)

Efficient multiple starting point optimization for automated analog circuit optimization via recycling simulation data. - Bo Peng; Fan Yang 001; Changhao Yan; Xuan Zeng 001; Dian Zhou (DATE, 2016)

Efficient Memory Partitioning for Parallel Data Access via Data Reuse. - Jincheng Su; Fan Yang 001; Xuan Zeng 001; Dian Zhou (FPGA, 2016)

A novel unified dummy fill insertion framework with SQP-based optimization method. - Yudong Tao; Changhao Yan; Yibo Lin; Sheng-Guo Wang; David Z. Pan; Xuan Zeng 001 (ICCAD, 2016)

Efficient statistical analysis for correlated rare failure events via asymptotic probability approximation. - Handi Yu; Jun Tao 001; Changhai Liao; Yangfeng Su; Dian Zhou; Xuan Zeng 001; Xin Li 001 (ICCAD, 2016)

Fast compressive sensing reconstruction algorithm on FPGA using Orthogonal Matching Pursuit. - Zhelun Yu; Jincheng Su; Fan Yang 001; Yangfeng Su; Xuan Zeng 001; Dian Zhou; Weiping Shi (ISCAS, 2016)

High-speed link verification based on statistical inference. - Xuan Zeng 001; Chenlei Fang; Qicheng Huang; Fan Yang 001; Dian Zhou; Wei Cai 003; Weiping Shi (ISCAS, 2016)

A yield-enhanced global optimization methodology for analog circuit based on extreme value theory. - Minghua Li; Guanming Huang; Xiulong Wu; Liuxi Qian; Xuan Zeng 001; Dian Zhou (Sci. China Inf. Sci., 2016)

A Memristor Crossbar-Based Computation Scheme with High Precision. - Junyi Li; Fulin Peng; Fan Yang 001; Xuan Zeng 001 (CoRR, 2016)

An aggregating based model order reduction method for power grids. - Qicheng Huang; Xiao Li 002; Chenlei Fang; Fan Yang 001; Yangfeng Su; Xuan Zeng 001 (Integr., 2016)

Efficient Hybrid Performance Modeling for Analog Circuits Using Hierarchical Shrinkage Priors. - Changhai Liao; Jun Tao 001; Handi Yu; Zhangwen Tang; Yangfeng Su; Dian Zhou; Xuan Zeng 001; Xin Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Efficient Spatial Variation Modeling of Nanoscale Integrated Circuits Via Hidden Markov Tree. - Changhai Liao; Jun Tao 001; Xuan Zeng 001; Yangfeng Su; Dian Zhou; Xin Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Harvesting Design Knowledge From the Internet: High-Dimensional Performance Tradeoff Modeling for Large-Scale Analog Circuits. - Jun Tao 001; Changhai Liao; Xuan Zeng 001; Xin Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography. - Yunfeng Yang; Wai-Shing Luk; David Z. Pan; Hai Zhou 001; Changhao Yan; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Parallel sparse LU decomposition using FPGA with an efficient cache architecture. - Xiang Ge; Hengliang Zhu; Fan Yang 001; Lingli Wang; Xuan Zeng 001 (ASICON, 2017)

An efficient algorithm for stencil planning and optimization in E-beam lithography. - Jiabei Ge; Changhao Yan; Hai Zhou 001; Dian Zhou; Xuan Zeng 001 (ASP-DAC, 2017)

Network flow based cut redistribution and insertion for advanced 1D layout design. - Ye Zhang 011; Wai-Shing Luk; Fan Yang 001; Changhao Yan; Hai Zhou 001; Dian Zhou; Xuan Zeng 001 (ASP-DAC, 2017)

Efficient Bayesian Yield Optimization Approach for Analog and SRAM Circuits. - Mengshuo Wang; Fan Yang 001; Changhao Yan; Xuan Zeng 001; Xiangdong Hu (DAC, 2017)

Subgradient based multiple-starting-point algorithm for non-smooth optimization of analog circuits. - Wenlong Lv; Fan Yang 001; Changhao Yan; Dian Zhou; Xuan Zeng 001 (DATE, 2017)

An efficient leakage-aware thermal simulation approach for 3D-ICs using corrected linearized model and algebraic multigrid. - Chao Yan; Hengliang Zhu; Dian Zhou; Xuan Zeng 001 (DATE, 2017)

Impact of circuit-level non-idealities on vision-based autonomous driving systems. - Handi Yu; Changhao Yan; Xuan Zeng 001; Xin Li 001 (ICCAD, 2017)

Efficient SVM-based hotspot detection using spectral clustering. - Fan Yang 001; Charles C. Chiang; Xuan Zeng 001; Dian Zhou (ISCAS, 2017)

Layout decomposition for hybrid E-beam and DSA double patterning lithography. - Yunfeng Yang; Fan Yang 001; Wai-Shing Luk; Changhao Yan; Xuan Zeng 001; Xiangdong Hu (ISCAS, 2017)

A grid-based detailed routing algorithm for advanced 1D process. - Ye Zhang 011; Fan Yang 001; Dian Zhou; Xuan Zeng 001; Xiangdong Hu (ISCAS, 2017)

Efficient spectral graph sparsification via Krylov-subspace based spectral perturbation analysis. - Shuhan Zhang; Fan Yang 001; Xuan Zeng 001; Dian Zhou; Shun Li; Xiangdong Hu (ISCAS, 2017)

A Novel N-Retry Transactional Memory Model for Multi-Thread Programming. - Kun Lu; Changhao Yan; Hai Zhou 001; Dian Zhou; Xuan Zeng 001 (ISPA/IUCC, 2017)

Hear the heart: Daily cardiac health monitoring using Ear-ECG and machine learning. - Qingxue Zhang; Dian Zhou; Xuan Zeng 001 (UEMCON, 2017)

PulsePrint: Single-arm-ECG biometric human identification using deep learning. - Qingxue Zhang; Dian Zhou; Xuan Zeng 001 (UEMCON, 2017)

Methodologies for layout decomposition and mask optimization: A systematic review. - Yuzhe Ma; Xuan Zeng 001; Bei Yu 001 (VLSI-SoC, 2017)

A Machine Learning-Empowered System for Long-Term Motion-Tolerant Wearable Monitoring of Blood Pressure and Heart Rate With Ear-ECG/PPG. - Qingxue Zhang; Xuan Zeng 001; Wenchuang Walter Hu; Dian Zhou (IEEE Access, 2017)

HeartID: A Multiresolution Convolutional Neural Network for ECG-Based Biometric Human Identification in Smart Health Applications. - Qingxue Zhang; Dian Zhou; Xuan Zeng 001 (IEEE Access, 2017)

An efficient and robust method to determine the optimal tap coefficients of high speed FIR equalizer. - Guanming Huang; Donesh Gillin; Dian Zhou; Jin Liu 004; Xuan Zeng 001; Po-Yu Kuo (Sci. China Inf. Sci., 2017)

A Novel Framework for Motion-Tolerant Instantaneous Heart Rate Estimation by Phase-Domain Multiview Dynamic Time Warping. - Qingxue Zhang; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Biomed. Eng., 2017)

Efficient Memory Partitioning for Parallel Data Access in FPGA via Data Reuse. - Jincheng Su; Fan Yang 001; Xuan Zeng 001; Dian Zhou; Jie Chen 002 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Improved Tangent Space-Based Distance Metric for Lithographic Hotspot Classification. - Fan Yang 001; Subarna Sinha; Charles C. Chiang; Xuan Zeng 001; Dian Zhou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

C-YES: An Efficient Parametric Yield Estimation Approach for Analog and Mixed-Signal Circuits Based on Multicorner-Multiperformance Correlations. - Wei Zeng; Hengliang Zhu; Xuan Zeng 001; Dian Zhou; Ruey-Wen Liu; Xin Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Optimization and Quality Estimation of Circuit Design via Random Region Covering Method. - Zhaori Bi; Dian Zhou; Sheng-Guo Wang; Xuan Zeng 001 (ACM Trans. Design Autom. Electr. Syst., 2017)

An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation. - Yunfeng Yang; Wai-Shing Luk; Hai Zhou 001; David Z. Pan; Dian Zhou; Changhao Yan; Xuan Zeng 001 (ACM Trans. Design Autom. Electr. Syst., 2017)

High-Dimensional and Multiple-Failure-Region Importance Sampling for SRAM Yield Analysis. - Mengshuo Wang; Changhao Yan; Xin Li 001; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Multi-objective bayesian optimization for analog/RF circuit synthesis. - Wenlong Lyu; Fan Yang 001; Changhao Yan; Dian Zhou; Xuan Zeng 001 (DAC, 2018)

A general graph based pessimism reduction framework for design optimization of timing closure. - Fulin Peng; Changhao Yan; Chunyang Feng; Jianquan Zheng; Sheng-Guo Wang; Dian Zhou; Xuan Zeng 001 (DAC, 2018)

An efficient data reuse strategy for multi-pattern data access. - Wensong Li; Fan Yang 001; Hengliang Zhu; Xuan Zeng 001; Dian Zhou (ICCAD, 2018)

Batch Bayesian Optimization via Multi-objective Acquisition Ensemble for Automated Analog Circuit Design. - Wenlong Lyu; Fan Yang 001; Changhao Yan; Dian Zhou; Xuan Zeng 001 (ICML, 2018)

Sparse VLSI Layout Feature Extraction: A Dictionary Learning Approach. - Hao Geng; Haoyu Yang; Bei Yu 001; Xingquan Li; Xuan Zeng 001 (ISVLSI, 2018)

A novel single-arm-worn 24 h heart disease monitor empowered by machine intelligence. - Qingxue Zhang; Dian Zhou; Xuan Zeng 001 (Biomed. Signal Process. Control., 2018)

A dual-output hardening design of inverter chain for P-hit single-event transient pulse elimination. - Changyong Liu; Chunyu Peng; Zhiting Lin; Xiulong Wu; Ziyang Chen; Qiang Zhao 007; Xuan Li; Junning Chen; Xuan Zeng 001; Xiangdong Hu (IEICE Electron. Express, 2018)

Offset voltage suppressed sense amplifier with self-adaptive distribution transformation technique. - Chunyu Peng; Lingyu Kong; Xiulong Wu; Zhiting Lin; Hua Xu; Junning Chen; Xuan Zeng 001 (IEICE Electron. Express, 2018)

Low-Power Noise-Immune Nanoscale Circuit Design Using Coding-Based Partial MRF Method. - Yan Li; Yufeng Li 003; I-Chyn Wey; Jianhao Hu; Fan Yang 001; Xuan Zeng 001; Xiaoxue Jiang; Jie Chen 002 (IEEE J. Solid State Circuits, 2018)

Efficient Yield Optimization for Analog and SRAM Circuits via Gaussian Process Regression and Adaptive Yield Estimation. - Mengshuo Wang; Wenlong Lv; Fan Yang 001; Changhao Yan; Wei Cai 003; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Smart-MSP: A Self-Adaptive Multiple Starting Point Optimization Approach for Analog Circuit Synthesis. - Yishi Yang; Hengliang Zhu; Zhaori Bi; Changhao Yan; Dian Zhou; Yangfeng Su; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Interlayer Cooling Network Design for High-Performance 3D ICs Using Channel Patterning and Pruning. - Hengliang Zhu; Feng Hu; Hao Zhou 008; David Z. Pan; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

An Efficient Bayesian Optimization Approach for Automated Optimization of Analog Circuits. - Wenlong Lyu; Pan Xue; Fan Yang 001; Changhao Yan; Zhiliang Hong; Xuan Zeng 001; Dian Zhou (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

An Efficient Non-Gaussian Sampling Method for High Sigma SRAM Yield Analysis. - Jinyuan Zhai; Changhao Yan; Sheng-Guo Wang; Dian Zhou; Hai Zhou 001; Xuan Zeng 001 (ACM Trans. Design Autom. Electr. Syst., 2018)

Feedback-Based Low-Power Soft-Error-Tolerant Design for Dual-Modular Redundancy. - Yan Li; Yufeng Li 003; Jie Han 001; Jianhao Hu; Fan Yang 001; Xuan Zeng 001; Bruce F. Cockburn; Jie Chen 002 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization. - Ye Zhang 011; Wenlong Lyu; Wai-Shing Luk; Fan Yang 001; Hai Zhou 001; Dian Zhou; David Z. Pan; Xuan Zeng 001 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs With a Novel Adaptive Strategy Finite Element Method. - Hao Zhou 008; Hengliang Zhu; Tao Cui; David Z. Pan; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Parallel Global Placement on CPU via Parallel Reduction. - Huaidong Gao; Fan Yang 001; Dian Zhou; Xuan Zeng 001 (ASICON, 2019)

Scheduling Algorithm Based on System of Difference Constraints Using Network Flow. - Hao Jiang; Yang Fan; Xuan Zeng 001 (ASICON, 2019)

Learning Sparse Patterns in Deep Neural Networks. - Weijing Wen; Fan Yang 001; Yangfeng Su; Dian Zhou; Xuan Zeng 001 (ASICON, 2019)

Faster Region-based Hotspot Detection. - Ran Chen 001; Wei Zhong; Haoyu Yang; Hao Geng; Xuan Zeng 001; Bei Yu 001 (DAC, 2019)

Efficient Layout Hotspot Detection via Binarized Residual Neural Network. - Yiyang Jiang; Fan Yang 001; Hengliang Zhu; Bei Yu 001; Dian Zhou; Xuan Zeng 001 (DAC, 2019)

An Efficient Multi-fidelity Bayesian Optimization Approach for Analog Circuit Synthesis. - Shuhan Zhang; Wenlong Lyu; Fan Yang 001; Changhao Yan; Dian Zhou; Xuan Zeng 001; Xiangdong Hu (DAC, 2019)

An Efficient FPGA-based Floating Random Walk Solver for Capacitance Extraction using SDAccel. - Xin Wei; Changhao Yan; Hai Zhou 001; Dian Zhou; Xuan Zeng 001 (DATE, 2019)

Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network. - Shuhan Zhang; Wenlong Lyu; Fan Yang 001; Changhao Yan; Dian Zhou; Xuan Zeng 001 (DATE, 2019)

Efficient Performance Trade-off Modeling for Analog Circuit based on Bayesian Neural Network. - Zhengqi Gao; Jun Tao 001; Fan Yang 001; Yangfeng Su; Dian Zhou; Xuan Zeng 001 (ICCAD, 2019)

A single event upset tolerant latch with parallel nodes. - Changyong Liu; Nianlong Liu; Zhiting Lin; Xiulong Wu; Chunyu Peng; Qiang Zhao 007; Xuan Li; Junning Chen; Xuan Zeng 001; Xiangdong Hu (IEICE Electron. Express, 2019)

An inverter chain with parallel output nodes for eliminating single-event transient pulse. - Changyong Liu; Zhiting Lin; Xiulong Wu; Chunyu Peng; Qiang Zhao 007; Xuan Li; Junning Chen; Xuan Zeng 001; Xiangdong Hu (IEICE Electron. Express, 2019)

Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization via SDP Relaxation. - Jun Tao 001; Yangfeng Su; Dian Zhou; Xuan Zeng 001; Xin Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

An Efficient Memory Partitioning Approach for Multi-Pattern Data Access via Data Reuse. - Wensong Li; Fan Yang 001; Hengliang Zhu; Xuan Zeng 001; Dian Zhou (ACM Trans. Reconfigurable Technol. Syst., 2019)

An Efficient FPGA Implementation of Orthogonal Matching Pursuit With Square-Root-Free QR Decomposition. - Xiang Ge; Fan Yang 001; Hengliang Zhu; Xuan Zeng 001; Dian Zhou (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application. - Chunyu Peng; Jiati Huang; Changyong Liu; Qiang Zhao 007; Songsong Xiao; Xiulong Wu; Zhiting Lin; Junning Chen; Xuan Zeng 001 (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Bayesian Methods for the Yield Optimization of Analog and SRAM Circuits. - Shuhan Zhang; Fan Yang 001; Dian Zhou; Xuan Zeng 001 (ASP-DAC, 2020)

An Efficient and Robust Yield Optimization Method for High-dimensional SRAM Circuits. - Xiaodong Wang; Tianchen Gu; Changhao Yan; Xiulong Wu; Fan Yang 001; Sheng-Guo Wang; Dian Zhou; Xuan Zeng 001 (DAC, 2020)

An Efficient Asynchronous Batch Bayesian Optimization Approach for Analog Circuit Synthesis. - Shuhan Zhang; Fan Yang 001; Dian Zhou; Xuan Zeng 001 (DAC, 2020)

An Efficient Bayesian Optimization Approach for Analog Circuit Synthesis via Sparse Gaussian Process Modeling. - Biao He; Shuhan Zhang; Fan Yang 001; Changhao Yan; Dian Zhou; Xuan Zeng 001 (DATE, 2020)

Hotspot Detection via Attention-based Deep Layout Metric Learning. - Hao Geng; Haoyu Yang; Lu Zhang; Jin Miao; Fan Yang 001; Xuan Zeng 001; Bei Yu 001 (ICCAD, 2020)

An Efficient Memory Partitioning Approach for Multi-Pattern Data Access in STT-RAM. - Binbin Liu; Fan Yang 001; Dian Zhou; Xuan Zeng 001 (ISCAS, 2020)

A Mixed-Variable Bayesian Optimization Approach for Analog Circuit Synthesis. - Jialin Lu; Shuhan Zhang; Fan Yang 001; Dian Zhou; Xuan Zeng 001 (ISCAS, 2020)

Multi-Corner Parametric Yield Estimation via Bayesian Inference on Bernoulli Distribution with Conjugate Prior. - Jiahe Shi; Zhengqi Gao; Jun Tao 001; Yangfeng Su; Dian Zhou; Xuan Zeng 001 (ISCAS, 2020)

Learning Low-Rank Structured Sparsity in Recurrent Neural Networks. - Weijing Wen; Fan Yang 001; Yangfeng Su; Dian Zhou; Xuan Zeng 001 (ISCAS, 2020)

Projection based Active Gaussian Process Regression for Pareto Front Modeling. - Zhengqi Gao; Jun Tao 001; Yangfeng Su; Dian Zhou; Xuan Zeng 001 (CoRR, 2020)

Nonlinear CNN: improving CNNs with quadratic convolutions. - Yiyang Jiang; Fan Yang 001; Hengliang Zhu; Dian Zhou; Xuan Zeng 001 (Neural Comput. Appl., 2020)

Efficient Rare Failure Analysis Over Multiple Corners via Correlated Bayesian Inference. - Zhengqi Gao; Jun Tao 001; Yangfeng Su; Dian Zhou; Xuan Zeng 001; Xin Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Efficient Parametric Yield Estimation Over Multiple Process Corners via Bayesian Inference Based on Bernoulli Distribution. - Zhengqi Gao; Jun Tao 001; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Efficient Statistical Analysis for Correlated Rare Failure Events via Asymptotic Probability Approximation. - Fulin Peng; Handi Yu; Jun Tao 001; Yangfeng Su; Dian Zhou; Xuan Zeng 001; Xin Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Improved Low-Power Cost-Effective DCT Implementation Based on Markov Random Field and Stochastic Logic. - Yufeng Li 003; Yan Li; I-Chyn Wey; Deqiang Cheng; Fan Yang 001; Xuan Zeng 001; Jie Chen 002 (IEEE Trans. Circuits Syst. Video Technol., 2020)

Analog/RF Post-silicon Tuning via Bayesian Optimization. - Renjian Pan; Jun Tao 001; Yangfeng Su; Dian Zhou; Xuan Zeng 001; Xin Li 001 (ACM Trans. Design Autom. Electr. Syst., 2020)

A Fast Aging-aware Static Timing Analysis Prediction Frame of Digital Integrated Circuits. - Jiahui Hu; Changhao Yan; Chao Guo; Ronggui Jiang; Dian Zhou; Xuan Zeng 001 (ASICON, 2021)

Efficient High-Level Synthesis of Approximate Computing Circuits via Multi-fidelity Modeling. - Yingqi Li; Fan Yang 001; Changhao Yan; Xuan Zeng 001 (ASICON, 2021)

High-Dimensional Bayesian Optimization for Automated Analog Circuit Design via Add-Graph Structure. - Yan Wang; Changhao Yan; Dian Zhou; Xuan Zeng 001 (ASICON, 2021)

Bayesian Inference on Introduced General Region: An Efficient Parametric Yield Estimation Method for Integrated Circuits. - Zhengqi Gao; Zihao Chen; Jun Tao 001; Yangfeng Su; Dian Zhou; Xuan Zeng 001 (ASP-DAC, 2021)

A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization. - Jiangli Huang; Fan Yang 001; Changhao Yan; Dian Zhou; Xuan Zeng 001 (ASP-DAC, 2021)

NeurFill: Migrating Full-Chip CMP Simulators to Neural Networks for Model-Based Dummy Filling Synthesis. - Junzhe Cai; Changhao Yan; Yuzhe Ma; Bei Yu 001; Dian Zhou; Xuan Zeng 001 (DAC, 2021)

Automated Compensation Scheme Design for Operational Amplifier via Bayesian Optimization. - Jialin Lu; Liangbo Lei; Fan Yang 001; Changhao Yan; Xuan Zeng 001 (DAC, 2021)

An Efficient Yield Estimation Method for Layouts of High Dimensional and High Sigma SRAM Arrays. - Yue Shen; Changhao Yan; Sheng-Guo Wang; Dian Zhou; Xuan Zeng 001 (DATE, 2021)

When Wafer Failure Pattern Classification Meets Few-shot Learning and Self-Supervised Learning. - Hao Geng; Fan Yang 001; Xuan Zeng 001; Bei Yu 001 (ICCAD, 2021)

Accelerate Logic Re-simulation on GPU via Gate/Event Parallelism and State Compression. - Cheng Zeng; Fan Yang 001; Xuan Zeng 001 (ICCAD, 2021)

Hotspot Detection via Multi-task Learning and Transformer Encoder. - Binwu Zhu; Ran Chen 001; Xinyun Zhang; Fan Yang 001; Xuan Zeng 001; Bei Yu 001; Martin D. F. Wong (ICCAD, 2021)

Bayesian Optimization Approach for Analog Circuit Design Using Multi-Task Gaussian Process. - Jiangli Huang; Shuhan Zhang; Cong Tao; Fan Yang 001; Changhao Yan; Dian Zhou; Xuan Zeng 001 (ISCAS, 2021)

An Efficient Batch Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-objective Acquisition Ensemble. - Shuhan Zhang; Fan Yang 001; Changhao Yan; Dian Zhou; Xuan Zeng 001 (CoRR, 2021)

A Novel and Unified Full-Chip CMP Model Aware Dummy Fill Insertion Framework With SQP-Based Optimization Method. - Junzhe Cai; Changhao Yan; Yudong Tao; Yibo Lin; Sheng-Guo Wang; David Z. Pan; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Efficient Layout Hotspot Detection via Binarized Residual Neural Network Ensemble. - Yiyang Jiang; Fan Yang 001; Bei Yu 001; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

A Novel and Efficient Bayesian Optimization Approach for Analog Designs with Multi-Testbench. - Jingyao Zhao; Changhao Yan; Zhaori Bi; Fan Yang 001; Xuan Zeng 001; Dian Zhou (ASP-DAC, 2022)

Floorplanning with graph attention. - Yiting Liu; Ziyi Ju; Zhengming Li; Mingzhi Dong; Hai Zhou 001; Jia Wang 003; Fan Yang 001; Xuan Zeng 001; Li Shang (DAC, 2022)

An efficient yield optimization method for analog circuits via gaussian process classification and varying-sigma sampling. - Xiaodong Wang; Changhao Yan; Fan Yang 001; Dian Zhou; Xuan Zeng 001 (DAC, 2022)

Topology Optimization of Operational Amplifier in Continuous Space via Graph Embedding. - Jialin Lu; Liangbo Lei; Fan Yang 001; Li Shang; Xuan Zeng 001 (DATE, 2022)

Efficient Hotspot Detection via Graph Neural Network. - Shuyuan Sun; Yiyang Jiang; Fan Yang 001; Bei Yu 001; Xuan Zeng 001 (DATE, 2022)

A High-Precision Stochastic Solver for Steady-State Thermal Analysis with Fourier Heat Transfer Robin Boundary Conditions. - Longlong Yang; Cuiyang Ding; Changhao Yan; Dian Zhou; Xuan Zeng 001 (ICCAD, 2022)

A Batch Bayesian Optimization Approach For Analog Circuit Synthesis Based On Multi-Points Selection Criterion. - Xu Fu; Changhao Yan; Zhaori Bi; Fan Yang 001; Dian Zhou; Xuan Zeng 001 (ISCAS, 2022)

SAT-based Scheduling Algorithm for High-level Synthesis Considering Resource Sharing. - Hao Jiang; Fan Yang 001; Changhao Yan; Xuan Zeng 001 (ISCAS, 2022)

Adversarial Sample Generation for Lithography Hotspot Detection. - Shuyuan Sun; Yiyang Jiang; Fan Yang 001; Xuan Zeng 001 (ISCAS, 2022)

LinEasyBO: Scalable Bayesian Optimization Approach for Analog Circuit Synthesis via One-Dimensional Subspaces. - Shuhan Zhang; Fan Yang 001; Changhao Yan; Dian Zhou; Xuan Zeng 001 (MLCAD, 2022)

Faster Region-Based Hotspot Detection. - Ran Chen 001; Wei Zhong; Haoyu Yang; Hao Geng; Fan Yang 001; Xuan Zeng 001; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Fast Statistical Analysis of Rare Failure Events With Truncated Normal Distribution in High-Dimensional Variation Space. - Zhengqi Gao; Jun Tao 001; Yangfeng Su; Dian Zhou; Xuan Zeng 001; Xin Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Hotspot Detection via Attention-Based Deep Layout Metric Learning. - Hao Geng; Haoyu Yang; Lu Zhang; Fan Yang 001; Xuan Zeng 001; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Correlated Rare Failure Analysis via Asymptotic Probability Evaluation. - Jun Tao 001; Handi Yu; Yangfeng Su; Dian Zhou; Xuan Zeng 001; Xin Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Analog Circuit Yield Optimization via Freeze-Thaw Bayesian Optimization Technique. - Xiaodong Wang; Changhao Yan; Yuzhe Ma; Bei Yu 001; Fan Yang 001; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

An Efficient Batch-Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multiobjective Acquisition Ensemble. - Shuhan Zhang; Fan Yang 001; Changhao Yan; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Learning From Highly Confident Samples for Automatic Knee Osteoarthritis Severity Assessment: Data From the Osteoarthritis Initiative. - Yifan Wang; Zhaori Bi; Yuxue Xie; Tao Wu; Xuan Zeng 001; Shuang Chen; Dian Zhou (IEEE J. Biomed. Health Informatics, 2022)

Efficient Layout Hotspot Detection via Neural Architecture Search. - Yiyang Jiang; Fan Yang 001; Bei Yu 001; Dian Zhou; Xuan Zeng 001 (ACM Trans. Design Autom. Electr. Syst., 2022)

A Parallel Iterative Probabilistic Method for Mixed Problems of Laplace Equations with the Feynman-Kac Formula of Killed Brownian Motions. - Cuiyang Ding; Changhao Yan; Xuan Zeng 001; Wei Cai 003 (SIAM J. Sci. Comput., 2022)

FPDsim: A Structural Simulator For Power Grid Analysis Of Flat Panel Display. - Chengtao An; Chunqiao Li; Xiangqi Li; Yangfeng Su; Fan Yang 001; Xuan Zeng 001 (DAC, 2023)

Efficient ILT via Multi-level Lithography Simulation. - Shuyuan Sun; Fan Yang 001; Bei Yu 001; Li Shang; Xuan Zeng 001 (DAC, 2023)

Automated Design of Complex Analog Circuits with Multiagent based Reinforcement Learning. - Jinxin Zhang; Jiarui Bao; Zhangcheng Huang 001; Xuan Zeng 001; Ye Lu 005 (DAC, 2023)

cVTS: A Constrained Voronoi Tree Search Method for High Dimensional Analog Circuit Synthesis. - Aidong Zhao; Xianan Wang; Zixiao Lin; Zhaori Bi; Xudong Li; Changhao Yan; Fan Yang 001; Li Shang; Dian Zhou; Xuan Zeng 001 (DAC, 2023)

Automated and Agile Design of Layout Hotspot Detector via Neural Architecture Search. - Zihao Chen; Fan Yang 001; Li Shang; Xuan Zeng 001 (DATE, 2023)

Sphinx: A Hybrid Boolean Processor-FPGA Hardware Emulation System. - Ruiyao Pu; Yiwei Sun; Pei-Hsin Ho; Fan Yang 001; Li Shang; Xuan Zeng 001 (ICCAD, 2023)

TOTAL: Topology Optimization of Operational Amplifier via Reinforcement Learning. - Zihao Chen; Songlei Meng; Fan Yang 001; Li Shang; Xuan Zeng 001 (ISQED, 2023)

An Analog Circuit Building Block Generator via Nested Multi-Fidelity Modeling. - Jiangli Huang; Chuyu Wang; Yuyang Yan; Cong Tao; Fan Yang 001; Changhao Yan; Wenchuang Walter Hu; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

ESPSim: An Efficient Scalable Power Grid Simulator Based on Parallel Algebraic Multigrid. - Chunqiao Li; Chengtao An; Fan Yang 001; Xuan Zeng 001 (ACM Trans. Design Autom. Electr. Syst., 2023)

Correlated Bayesian Model Fusion: Efficient High-Dimensional Performance Modeling of Analog/RF Integrated Circuits Over Multiple Corners. - Zhengqi Gao; Fa Wang; Jun Tao 001; Yangfeng Su; Xuan Zeng 001; Xin Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A Batched Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-Fidelity Modeling. - Biao He; Shuhan Zhang; Yifan Wang; Tianning Gao; Fan Yang 001; Changhao Yan; Dian Zhou; Zhaori Bi; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A path integral Monte Carlo (PIMC) method based on Feynman-Kac formula for electrical impedance tomography. - Cuiyang Ding; Yijing Zhou; Wei Cai 003; Xuan Zeng 001; Changhao Yan (J. Comput. Phys., 2023)

GraphPlanner: Floorplanning with Graph Neural Network. - Yiting Liu; Ziyi Ju; Zhengming Li; Mingzhi Dong; Hai Zhou 001; Jia Wang 003; Fan Yang 001; Xuan Zeng 001; Li Shang (ACM Trans. Design Autom. Electr. Syst., 2023)

Unleashing the Power of Graph Spectral Sparsification for Power Grid Analysis via Incomplete Cholesky Factorization. - Chunqiao Li; Chengtao An; Zhengqi Gao; Fan Yang 001; Yangfeng Su; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Automatic Op-Amp Generation From Specification to Layout. - Jialin Lu; Liangbo Lei; Jiangli Huang; Fan Yang 001; Li Shang; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

High-Level Topology Synthesis Method for Δ-Σ Modulators via Bi-Level Bayesian Optimization. - Jialin Lu; Yijie Li; Fan Yang 001; Li Shang; Xuan Zeng 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

MACRO: Multi-agent Reinforcement Learning-based Cross-layer Optimization of Operational Amplifier. - Zihao Chen; Songlei Meng; Fan Yang 001; Li Shang; Xuan Zeng 001 (ASPDAC, 2024)

A Study on Exploring and Exploiting the High-dimensional Design Space for Analog Circuit Design Automation : (Invited Paper). - Ruiyu Lyu; Yuan Meng; Aidong Zhao; Zhaori Bi; Keren Zhu 001; Fan Yang 001; Changhao Yan; Dian Zhou; Xuan Zeng 001 (ASPDAC, 2024)

Asynchronous Batch Constrained Multi-Objective Bayesian Optimization for Analog Circuit Sizing. - Xuyang Zhao; Zhaori Bi; Changhao Yan; Fan Yang 001; Ye Lu 005; Dian Zhou; Xuan Zeng 001 (ASPDAC, 2024)

Artisan: Automated Operational Amplifier Design via Domain-specific Large Language Model. - Zihao Chen; Jiangli Huang; Yiting Liu; Fan Yang 001; Li Shang; Dian Zhou; Xuan Zeng 001 (DAC, 2024)

HiMOSS: A Novel High-dimensional Multi-objective Optimization Method via Adaptive Gradient-Based Subspace Sampling for Analog Circuit Sizing. - Tianchen Gu; Ruiyu Lyu; Zhaori Bi; Changhao Yan; Fan Yang 001; Dian Zhou; Tao Cui; Xin Liu 001; Zaikun Zhang; Xuan Zeng 001 (DAC, 2024)

EVDMARL: Efficient Value Decomposition-based Multi-Agent Reinforcement Learning with Domain-Randomization for Complex Analog Circuit Design Migration. - Handa Sun; Zhaori Bi; Wenning Jiang; Ye Lu 005; Changhao Yan; Fan Yang 001; Wenchuang Hu; Sheng-Guo Wang; Dian Zhou; Xuan Zeng 001 (DAC, 2024)

Efficient ILT via Multigrid-Schwartz Method. - Shuyuan Sun; Fan Yang 001; Bei Yu 001; Li Shang; Dian Zhou; Xuan Zeng 001 (DAC, 2024)

tSS-BO: Scalable Bayesian Optimization for Analog Circuit Sizing via Truncated Subspace Sampling. - Tianchen Gu; Jiaqi Wang; Zhaori Bi; Changhao Yan; Fan Yang 001; Yajie Qin; Tao Cui; Xuan Zeng 001 (DATE, 2024)

Circuits Physics Constrained Predictor of Static IR Drop with Limited Data. - Yuan Meng; Ruiyu Lyu; Zhaori Bi; Changhao Yan; Fan Yang 001; Wenchuang Hu; Dian Zhou; Xuan Zeng 001 (DATE, 2024)

A Semi-Tensor Product based Circuit Simulation for SAT-sweeping. - Hongyang Pan; Ruibing Zhang; Yinshui Xia; Lunyao Wang; Fan Yang 001; Xuan Zeng 001; Zhufei Chu (DATE, 2024)

AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis. - Jintao Li; Haochang Zhi; Ruiyu Lyu; Wangzhen Li; Zhaori Bi; Keren Zhu 001; Yanhan Zeng; Weiwei Shan; Changhao Yan; Fan Yang 001; Yun Li 002; Xuan Zeng 001 (ICCAD, 2024)

The Power of Graph Signal Processing for Chip Placement Acceleration. - Yiting Liu; Hai Zhou 001; Jia Wang 003; Fan Yang 001; Xuan Zeng 001; Li Shang (ICCAD, 2024)

Revisiting sensitivity-based analog sizing with derivative-aware Bayesian optimization and error-suppressed adjoint analysis. - Ruiyu Lyu; Aidong Zhao; Yuan Meng; Keren Zhu 001; Zhaori Bi; Changhao Yan; Fan Yang 001; Dian Zhou; Xuan Zeng 001 (ICCAD, 2024)

Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement. - Hongyang Pan; Cunqing Lan; Yiting Liu; Zhiang Wang; Li Shang; Xuan Zeng 001; Fan Yang 001; Keren Zhu 001 (ICCAD, 2024)

Exploring High-dimensional Search Space via Voronoi Graph Traversing. - Aidong Zhao; Xuyang Zhao; Tianchen Gu; Zhaori Bi; Xinwei Sun 001; Changhao Yan; Fan Yang 001; Dian Zhou; Xuan Zeng 001 (UAI, 2024)

Large circuit models: opportunities and challenges. - Lei Chen; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Ru Huang 001; Yu Huang 005; Sadaf Khan; Min Li; Xingquan Li; Yu Li; Yun Liang 001; et al. (Sci. China Inf. Sci., 2024)

Erratum to: Large circuit models: opportunities and challenges. - Lei Chen; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Ru Huang 001; Yu Huang 005; Sadaf Khan; Min Li; Xingquan Li; Yu Li; Yun Liang 001; et al. (Sci. China Inf. Sci., 2024)

Yield Optimization for Analog Circuits over Multiple Corners via Bayesian Neural Networks: Enhancing Circuit Reliability under Environmental Variation. - Nanlin Guo; Fulin Peng; Jiahe Shi; Fan Yang 001; Jun Tao 001; Xuan Zeng 001 (ACM Trans. Design Autom. Electr. Syst., 2024)

pNeurFill: Enhanced Neural Network Model-Based Dummy Filling Synthesis With Perimeter Adjustment. - Zhaoting Chen; Junzhe Cai; Changhao Yan; Zhaori Bi; Yuzhe Ma; Bei Yu 001; Wenchuang Walter Hu; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

BBGP-sDFO: Batch Bayesian and Gaussian Process Enhanced Subspace Derivative Free Optimization for High-Dimensional Analog Circuit Synthesis. - Tianchen Gu; Wangzhen Li; Aidong Zhao; Zhaori Bi; Xudong Li; Fan Yang 001; Changhao Yan; Wenchuang Walter Hu; Dian Zhou; Tao Cui; Xin Liu 001; Zaikun Zhang; et al. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

GNN-Cap: Chip-Scale Interconnect Capacitance Extraction Using Graph Neural Network. - Lihao Liu; Fan Yang 001; Li Shang; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

D3PBO: Dynamic Domain Decomposition-based Parallel Bayesian Optimization for Large-scale Analog Circuit Sizing. - Aidong Zhao; Tianchen Gu; Zhaori Bi; Fan Yang 001; Changhao Yan; Xuan Zeng 001; Zixiao Lin; Wenchuang Walter Hu; Dian Zhou (ACM Trans. Design Autom. Electr. Syst., 2024)

Hierarchical Graph Learning-Based Floorplanning With Dirichlet Boundary Conditions. - Yiting Liu; Hai Zhou 001; Jia Wang 003; Fan Yang 001; Xuan Zeng 001; Li Shang (IEEE Trans. Very Large Scale Integr. Syst., 2024)

ROI-HIT: Region of Interest-Driven High-Dimensional Microarchitecture Design Space Exploration. - Xuyang Zhao; Tianning Gao; Aidong Zhao; Zhaori Bi; Changhao Yan; Fan Yang 001; Sheng-Guo Wang; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Multiagent Based Reinforcement Learning (MA-RL): An Automated Designer for Complex Analog Circuits. - Jiarui Bao; Jinxin Zhang; Zhangcheng Huang 001; Zhaori Bi; Xingwei Feng; Xuan Zeng 001; Ye Lu 005 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

ELMap: Area-Driven LUT Mapping with $k$-LUT Network Exact Synthesis. - Hongyang Pan; Keren Zhu 001; Fan Yang 001; Zhufei Chu; Xuan Zeng 001 (DATE, 2025)

INTO-OA: Interpretable Topology Optimization for Operational Amplifiers. - Jinyi Shen; Fan Yang 001; Li Shang; Zhaori Bi; Changhao Yan; Dian Zhou; Xuan Zeng 001 (DATE, 2025)

DAMIL-DCIM: A Digital CIM Layout Synthesis Framework with Dataflow-Aware Floorplan and MILP-Based Detailed Placement. - Chuyu Wang; Ke Hu; Fan Yang 001; Keren Zhu 001; Xuan Zeng 001 (DATE, 2025)

Robust analog/RF circuit design via Cycle-Consistent Generative Adversarial Networks. - Nanlin Guo; Jun Tao 001; Xuan Zeng 001; Xin Li 001 (Integr., 2025)

ATOM: An Automatic Topology Synthesis Framework for Operational Amplifiers. - Jinyi Shen; Fan Yang 001; Li Shang; Changhao Yan; Zhaori Bi; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Prior-Boosted GRL: Microarchitecture Design Space Exploration via Graph Representation Learning. - Zheng Wu; Jinyi Shen; Xiaoling Yi; Li Shang; Fan Yang 001; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

VTSMOC: An Efficient Voronoi Tree Search Boosted Multiobjective Bayesian Optimization With Constraints for High-Dimensional Analog Circuit Synthesis. - Aidong Zhao; Ruiyu Lyu; Xuyang Zhao; Zhaori Bi; Fan Yang 001; Changhao Yan; Dian Zhou; Yangfeng Su; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

pPIRW: An Efficient and Accurate Precalculation Path Integral Random Walk Solver for Steady-State Thermal Simulation With Robin Boundary Conditions. - Zhixuan Dong; Longlong Yang; Cuiyang Ding; Changhao Yan; Zhaori Bi; Sheng-Guo Wang; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Hierarchical Integration of Reinforcement Learning and Optimization Algorithms for Time-Efficient Design Automation of Complex Analog Circuit. - Xingwei Feng; Yifan Xu; Zhangcheng Huang 001; Wuyi Xu; Zhaori Bi; Fan Yang 001; Xuan Zeng 001; Ye Lu 005 (ACM Trans. Design Autom. Electr. Syst., 2025)

APPLE-DSE: Asynchronous Parallel Pareto Set Learning for Microarchitecture Design Space Exploration. - Xuyang Zhao; Tianning Gao; Zheng Wu; Zhaori Bi; Changhao Yan; Fan Yang 001; Sheng-Guo Wang; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

AnalogSeeker: An Open-source Foundation Language Model for Analog Circuit Design. - Zihao Chen; Ji Zhuang; Jinyi Shen; Xiaoyue Ke; Xinyi Yang; Mingjie Zhou; Zhuoyao Du; Xu Yan; Zhouyang Wu; Zhenyu Xu; Jiangli Huang; Li Shang; et al. (CoRR, 2025)