Clocking circuits for a 16Gb/s memory interface. - Ting Wu 003; Xudong Shi 004; Kambiz Kaviani; Haechang Lee; Jung-Hoon Chun; T. J. Chin; Jie Shen 010; Rich Perego; Ken Chang (CICC, 2008)

A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface. - Haechang Lee; Kun-Yung Ken Chang; Jung-Hoon Chun; Ting Wu 003; Yohan Frans; Brian S. Leibowitz; Nhat Nguyen; T. J. Chin; Kambiz Kaviani; Jie Shen 010; Xudong Shi 004; Wendemagegnehu T. Beyene; et al. (IEEE J. Solid State Circuits, 2009)

A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface. - Kambiz Kaviani; Ting Wu 003; Jason Wei; Amir Amirkhany; Jie Shen 010; T. J. Chin; Chintan Thakkar; Wendemagegnehu T. Beyene; Norman Chan; Catherine Chen 005; Bing Ren Chuang; Deborah Dressler; et al. (IEEE J. Solid State Circuits, 2012)