A pipelined architecture for normal I/O order FFT. - Xue Liu 003; Feng Yu 003; Ze-ke Wang (J. Zhejiang Univ. Sci. C, 2011)

Block Processor: A resource-distributed architecture. - Ze-ke Wang; Feng Yu 003; Xue Liu 003 (HPEC, 2013)

High-speed, fixed-latency serial links with Xilinx FPGAs. - Xue Liu 003; Qing-xu Deng; Bo-ning Hou; Ze-ke Wang (J. Zhejiang Univ. Sci. C, 2014)

A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT. - Ze-ke Wang; Xue Liu 003; Bingsheng He; Feng Yu 003 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Design and FPGA Implementation of a Reconfigurable 1024-Channel Channelization Architecture for SDR Application. - Xue Liu 003; Ze-ke Wang; Qing-xu Deng (IEEE Trans. Very Large Scale Integr. Syst., 2016)

FPGA implementation of a reconfigurable channelization for simultaneous multichannel DRM30/FM receiver. - Xue Liu 003; Ze-ke Wang; Qingxu Deng (IEEE Trans. Consumer Electron., 2017)

Design and FPGA Implementation of a Reconfigurable Digital Down Converter for Wideband Applications. - Xue Liu 003; Xin-Xin Yan; Ze-ke Wang; Qingxu Deng (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Hebe: An Order-Oblivious and High-Performance Execution Scheme for Conjunctive Predicates. - Ze-ke Wang; Kai Zhang 006; Haihang Zhou; Xue Liu 003; Bingsheng He (ICDE, 2018)

Boyi: A Systematic Framework for Automatically Deciding the Right Execution Model of OpenCL Applications on FPGAs. - Jiantong Jiang; Zeke Wang; Xue Liu 003; Juan Gómez-Luna; Nan Guan; Qingxu Deng; Wei Zhang 012; Onur Mutlu (FPGA, 2020)

Understanding and Optimizing Conjunctive Predicates Under Memory-Efficient Storage Layouts. - Ze-ke Wang; Xue Liu 003; Kai Zhang 006; Haihang Zhou; Bingsheng He (IEEE Trans. Knowl. Data Eng., 2021)