Design and Implementation a TPM Chip SUP320 by SOC. - Jiangchun Ren; Kui Dai; Zhiying Wang 003; Xue-mi Zhao; Yuan-man Tong (SEC, 2005)

Power Optimization of Interconnection Networks for Transport Triggered Architecture. - Xue-mi Zhao; Zhiying Wang (ESA, 2006)

A 6.35Mbps 1024-bit RSA crypto coprocessor in a 0.18um CMOS technology. - Xue-mi Zhao; Zhiying Wang 003; Hongyi Lu; Kui Dai (VLSI-SoC, 2006)

Design of a Low-Power Embedded Processor Architecture Using Asynchronous Function Units. - Yong Li 006; Zhiying Wang 003; Xue-mi Zhao; Jian Ruan; Kui Dai (Asia-Pacific Computer Systems Architecture Conference, 2007)