Distributed Control Independence for Composable Multi-processors. - Mengjie Mao; Hong An; Tao Sun; Qi Li 034; Bobin Deng; Xuechao Wei; Junrui Zhou (ACIS-ICIS, 2012)

Distributed replay protocol for distributed uniprocessors. - Mengjie Mao; Hong An; Bobin Deng; Tao Sun; Xuechao Wei; Wei Zhou; Wenting Han (ICS, 2012)

FlexBFS: a parallelism-aware implementation of breadth-first search on GPU. - Gu Liu; Hong An; Wenting Han; Xiaoqiang Li; Tao Sun; Wei Zhou; Xuechao Wei; Xulong Tang (PPoPP, 2012)

Throughput optimization for streaming applications on CPU-FPGA heterogeneous systems. - Xuechao Wei; Yun Liang 001; Tao Wang 004; Songwu Lu; Jason Cong (ASP-DAC, 2017)

Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs. - Xuechao Wei; Cody Hao Yu; Peng Zhang 007; Youxiang Chen; Yuxin Wang; Han Hu; Yun Liang 001; Jason Cong (DAC, 2017)

TGPA: tile-grained pipeline architecture for low latency CNN inference. - Xuechao Wei; Yun Liang 001; Xiuhong Li; Cody Hao Yu; Peng Zhang 007; Jason Cong (ICCAD, 2018)

Overcoming Data Transfer Bottlenecks in FPGA-based DNN Accelerators via Layer Conscious Memory Management. - Xuechao Wei; Yun Liang 001; Jason Cong (DAC, 2019)

Overcoming Data Transfer Bottlenecks in DNN Accelerators via Layer-Conscious Memory Managment. - Xuechao Wei; Yun Liang 001; Peng Zhang 007; Cody Hao Yu; Jason Cong (FPGA, 2019)

Frequency Improvement of Systolic Array-Based CNNs on FPGAs. - Jiaxi Zhang 001; Wentai Zhang 001; Guojie Luo; Xuechao Wei; Yun Liang 001; Jason Cong (ISCAS, 2019)

FTDL: A Tailored FPGA-Overlay for Deep Learning with High Scalability. - Runbin Shi; Yuhao Ding; Xuechao Wei; He Li 008; Hang Liu 001; Hayden Kwok-Hay So; Caiwen Ding (DAC, 2020)

FTDL: An FPGA-tailored Architecture for Deep Learning Systems. - Runbin Shi; Yuhao Ding; Xuechao Wei; Hang Liu 001; Hayden Kwok-Hay So; Caiwen Ding (FPGA, 2020)

Generating Systolic Array Accelerators With Reusable Blocks. - Liancheng Jia; Liqiang Lu; Xuechao Wei; Yun Liang 001 (IEEE Micro, 2020)

GCNear: A Hybrid Architecture for Efficient GCN Training with Near-Memory Processing. - Zhe Zhou 002; Cong Li; Xuechao Wei; Guangyu Sun 003 (CoRR, 2021)

GNNear: Accelerating Full-Batch Training of Graph Neural Networks with near-Memory Processing. - Zhe Zhou 002; Cong Li; Xuechao Wei; Xiaoyang Wang 006; Guangyu Sun 003 (PACT, 2022)

2022 ICCAD CAD Contest Problem C: Microarchitecture Design Space Exploration. - Sicheng Li 001; Chen Bai; Xuechao Wei; Bizhao Shi; Yen-Kuang Chen; Yuan Xie 001 (ICCAD, 2022)

PetS: A Unified Framework for Parameter-Efficient Transformers Serving. - Zhe Zhou 002; Xuechao Wei; Jiejing Zhang; Guangyu Sun 003 (USENIX ATC, 2022)

Klotski: DNN Model Orchestration Framework for Dataflow Architecture Accelerators. - Chen Bai; Xuechao Wei; Youwei Zhuo; Yi Cai 003; Hongzhong Zheng; Bei Yu 001; Yuan Xie 001 (ICCAD, 2023)

ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis. - Chen Bai; Jiayi Huang 001; Xuechao Wei; Yuzhe Ma; Sicheng Li 001; Hongzhong Zheng; Bei Yu 001; Yuan Xie 001 (MICRO, 2023)

Efficient Super-Resolution System With Block-Wise Hybridization and Quantized Winograd on FPGA. - Bizhao Shi; Jiaxi Zhang 001; Zhuolun He; Xuechao Wei; Sicheng Li 001; Guojie Luo; Hongzhong Zheng; Yuan Xie 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

An Intermediate-Centric Dataflow for Transposed Convolution Acceleration on FPGA. - Zhengzheng Ma; Tuo Dai; Xuechao Wei; Guojie Luo (ACM Trans. Embed. Comput. Syst., 2023)

PT-Map: Efficient Program Transformation Optimization for CGRA Mapping. - Bizhao Shi; Tuo Dai; Jiaxi Zhang 001; Xuechao Wei; Guojie Luo (DAC, 2024)

RadiK: Scalable and Optimized GPU-Parallel Radix Top-K Selection. - Yifei Li; Bole Zhou; Jiejing Zhang; Xuechao Wei; Yinghan Li; Yingda Chen (ICS, 2024)

ArkVale: Efficient Generative LLM Inference with Recallable Key-Value Eviction. - Renze Chen; Zhuofeng Wang; Beiquan Cao; Tong Wu; Size Zheng 001; Xiuhong Li; Xuechao Wei; Shengen Yan; Meng Li 004; Yun Liang 001 (NeurIPS, 2024)

POSTER: RadiK: Scalable Radix Top-K Selection on GPUs. - Yifei Li; Bole Zhou; Jiejing Zhang; Xuechao Wei; Yinghan Li; Yingda Chen (PPoPP, 2024)

Klotski v2: Improved DNN Model Orchestration Framework for Dataflow Architecture Accelerators. - Chen Bai; Xuechao Wei; Youwei Zhuo; Yi Cai 003; Hongzhong Zheng; Bei Yu 001; Yuan Xie 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)