Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design. - Yu Cao 001; Chenming Hu; Xuejue Huang; Andrew B. Kahng; Sudhakar Muddu; Dirk Stroobandt; Dennis Sylvester (ICCAD, 2000)

Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion. - Yu Cao 001; Xuejue Huang; Chenming Hu; Norman Chang; Shen Lin; O. Sam Nakagawa; Weize Xie (ISQED, 2001)

Loop-based interconnect modeling and optimization approach for multi-GHz clock network design. - Xuejue Huang; Phillip J. Restle; Thomas J. Bucelot; Yu Cao 001; Tsu-Jae King 001 (CICC, 2002)

Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion. - Yu Cao 001; Xuejue Huang; N. H. Chang; Shen Lin; O. Sam Nakagawa; Weize Xie; Dennis Sylvester; Chenming Hu (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Frequency-independent equivalent-circuit model for on-chip spiral inductors. - Yu Cao 001; Robert A. Groves; Xuejue Huang; Noah Zamdmer; Jean-Olivier Plouchart; Richard A. Wachnik; Tsu-Jae King 001; Chenming Hu (IEEE J. Solid State Circuits, 2003)

Loop-based interconnect modeling and optimization approach for multigigahertz clock network design. - Xuejue Huang; Phillip J. Restle; Thomas J. Bucelot; Yu Cao 001; Tsu-Jae King 001; Chenming Hu (IEEE J. Solid State Circuits, 2003)

Improved a priori interconnect predictions and technology extrapolation in the GTX system. - Yu Cao 001; Chenming Hu; Xuejue Huang; Andrew B. Kahng; Igor L. Markov; Michael Oliver; Dirk Stroobandt; Dennis Sylvester (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design. - Yu Cao 001; Xuejue Huang; Dennis Sylvester; Tsu-Jae King 001; Chenming Hu (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Switch-factor based loop RLC modeling for efficient timing analysis. - Yu Cao 001; Xiaodong Yang; Xuejue Huang; Dennis Sylvester (IEEE Trans. Very Large Scale Integr. Syst., 2005)