Code-independent output impedance: A new approach to increasing the linearity of current-steering DACs. - Xueqing Li 002; Qi Wei 001; Huazhong Yang (ICECS, 2011)

Balanced Switching Schemes for Gradient-Error Compensation in Current-Steering DACs. - Xueqing Li 002; Qi Wei 001; Fei Qiao; Huazhong Yang (IEICE Trans. Electron., 2012)

Steep Slope Devices: Enabling New Architectural Paradigms. - Karthik Swaminathan; Huichu Liu; Xueqing Li 002; Moon Seok Kim; Jack Sampson; Vijaykrishnan Narayanan (DAC, 2014)

Tunnel FET-based ultra-low power, low-noise amplifier design for bio-signal acquisition. - Huichu Liu; Mahsa Shoaran; Xueqing Li 002; Suman Datta; Alexandre Schmid; Vijaykrishnan Narayanan (ISLPED, 2014)

A Low-Voltage Low-Power LC Oscillator Using the Diode-Connected SymFET. - Xueqing Li 002; Wei-Yu Tsai; Huichu Liu; Suman Datta; Vijaykrishnan Narayanan (ISVLSI, 2014)

Independently-Controlled-Gate FinFET 6T SRAM Cell Design for Leakage Current Reduction and Enhanced Read Access Speed. - Kaisheng Ma; Huichu Liu; Yang Xiao 002; Yang Zheng; Xueqing Li 002; Sumeet Kumar Gupta; Yuan Xie 001; Vijaykrishnan Narayanan (ISVLSI, 2014)

Rf-powered systems using steep-slope devices. - Xueqing Li 002; Unsuk Dennis Heo; Kaisheng Ma; Vijaykrishnan Narayanan; Huichu Liu; Suman Datta (NEWCAS, 2014)

Understanding the landscape of accelerators for vision. - Nandhini Chandramoorthy; Karthik Swaminathan; Matthew Cotter; Xueqing Li 002; Indranil Palit; Xiaobo Sharon Hu; Michael T. Niemier; Kevin M. Irick (SiPS, 2014)

Low-power high-speed current mode logic using Tunnel-FETs. - Wei-Yu Tsai; Huichu Liu; Xueqing Li 002; Vijaykrishnan Narayanan (VLSI-SoC, 2014)

Tunnel FET RF Rectifier Design for Energy Harvesting Applications. - Huichu Liu; Xueqing Li 002; Ramesh Vaddi; Kaisheng Ma; Suman Datta; Vijaykrishnan Narayanan (IEEE J. Emerg. Sel. Topics Circuits Syst., 2014)

A 14 Bit 500 MS/s CMOS DAC Using Complementary Switched Current Sources and Time-Relaxed Interleaving DRRZ. - Xueqing Li 002; Qi Wei 001; Zhen Xu; Jianan Liu; Hui Wang 004; Huazhong Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Self-powered wearable sensor node: Challenges and opportunities. - Yongpan Liu; Hehe Li; Xueqing Li 002; Chun Jason Xue; Yuan Xie 001; Huazhong Yang (CASES, 2015)

Ambient energy harvesting nonvolatile processors: from circuit to system. - Yongpan Liu; Zewei Li; Hehe Li; Yiqun Wang; Xueqing Li 002; Kaisheng Ma; Shuangchen Li; Meng-Fan Chang; John Sampson; Yuan Xie 001; Jiwu Shu; Huazhong Yang (DAC, 2015)

Architecture exploration for ambient energy harvesting nonvolatile processors. - Kaisheng Ma; Yang Zheng; Shuangchen Li; Karthik Swaminathan; Xueqing Li 002; Yongpan Liu; Jack Sampson; Yuan Xie 001; Vijaykrishnan Narayanan (HPCA, 2015)

Dynamic Machine Learning Based Matching of Nonvolatile Processor Microarchitecture to Harvested Energy Profile. - Kaisheng Ma; Xueqing Li 002; Yongpan Liu; John Sampson; Yuan Xie 001; Vijaykrishnan Narayanan (ICCAD, 2015)

A 14-bit 1.0-GS/s dynamic element matching DAC with >80 dB SFDR up to the Nyquist. - Jianan Liu; Xueqing Li 002; Qi Wei 001; Huazhong Yang (ISCAS, 2015)

Using Multiple-Input NEMS for Parallel A/D Conversion and Image Processing. - Kaisheng Ma; Nandhini Chandramoorthy; Xueqing Li 002; Sumeet Kumar Gupta; John Sampson; Yuan Xie 001; Vijaykrishnan Narayanan (ISVLSI, 2015)

A High-Efficiency Switched-Capacitance HTFET Charge Pump for Low-Input-Voltage Applications. - Unsuk Heo; Xueqing Li 002; Huichu Liu; Sumeet Kumar Gupta; Suman Datta; Vijaykrishnan Narayanan (VLSID, 2015)

Nonvolatile Processor Architecture Exploration for Energy-Harvesting Applications. - Kaisheng Ma; Xueqing Li 002; Shuangchen Li; Yongpan Liu; John (Jack) Morgan Sampson; Yuan Xie 001; Vijaykrishnan Narayanan (IEEE Micro, 2015)

Nonvolatile memory design based on ferroelectric FETs. - Sumitha George; Kaisheng Ma; Ahmedullah Aziz; Xueqing Li 002; Asif Islam Khan; Sayeef S. Salahuddin; Meng-Fan Chang; Suman Datta; John Sampson; Sumeet Kumar Gupta; Vijaykrishnan Narayanan (DAC, 2016)

Device Circuit Co Design of FEFET Based Logic for Low Voltage Processors. - Sumitha George; Ahmedullah Aziz; Xueqing Li 002; Moon Seok Kim; Suman Datta; John Sampson; Sumeet Kumar Gupta; Vijaykrishnan Narayanan (ISVLSI, 2016)

Enabling Internet-of-Things with Opportunities Brought by Emerging Devices, Circuits and Architectures. - Xueqing Li 002; Kaisheng Ma; Sumitha George; John Sampson; Vijaykrishnan Narayanan (VLSI-SoC (Selected Papers), 2016)

Comparative Area and Parasitics Analysis in FinFET and Heterojunction Vertical TFET Standard Cells. - Moon Seok Kim; William Cane-Wissing; Xueqing Li 002; Jack Sampson; Suman Datta; Sumeet Kumar Gupta; Vijaykrishnan Narayanan (ACM J. Emerg. Technol. Comput. Syst., 2016)

Nonvolatile Processor Architectures: Efficient, Reliable Progress with Unstable Power. - Kaisheng Ma; Xueqing Li 002; Karthik Swaminathan; Yang Zheng; Shuangchen Li; Yongpan Liu; Yuan Xie 001; John (Jack) Morgan Sampson; Vijaykrishnan Narayanan (IEEE Micro, 2016)

Solar Power Prediction Assisted Intra-task Scheduling for Nonvolatile Sensor Nodes. - Daming Zhang; Yongpan Liu; Jinyang Li 002; Chun Jason Xue; Xueqing Li 002; Yu Wang 002; Huazhong Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Enabling New Computation Paradigms with HyperFET - An Emerging Device. - Wei-Yu Tsai; Xueqing Li 002; Matthew Jerry; Baihua Xie; Nikhil Shukla; Huichu Liu; Nandhini Chandramoorthy; Matthew Cotter; Arijit Raychowdhury; Donald M. Chiarulli; Steven P. Levitan; Suman Datta; et al. (IEEE Trans. Multi Scale Comput. Syst., 2016)

Exploration of Low-Power High-SFDR Current-Steering D/A Converter Design Using Steep-Slope Heterojunction Tunnel FETs. - Moon Seok Kim; Xueqing Li 002; Huichu Liu; John Sampson; Suman Datta; Vijaykrishnan Narayanan (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Spendthrift: Machine learning based resource and frequency scaling for ambient energy harvesting nonvolatile processors. - Kaisheng Ma; Xueqing Li 002; Srivatsa Rangachar Srinivasa; Yongpan Liu; John Sampson; Yuan Xie 001; Vijaykrishnan Narayanan (ASP-DAC, 2017)

Nonvolatile processors: Why is it trending? - Fang Su; Kaisheng Ma; Xueqing Li 002; Tongda Wu; Yongpan Liu; Vijaykrishnan Narayanan (DATE, 2017)

Harnessing ferroelectrics for non-volatile memories and logic. - Sumeet Kumar Gupta; Danni Wang; Sumitha George; Ahmedullah Aziz; Xueqing Li 002; Suman Datta; Vijaykrishnan Narayanan (ISQED, 2017)

Evaluating tradeoffs in granularity and overheads in supporting nonvolatile execution semantics. - Kaisheng Ma; Minli Julie Liao; Xueqing Li 002; Zhixuan Huan; Jack Sampson (ISQED, 2017)

Improving FPGA Design with Monolithic 3D Integration Using High Dense Inter-Stack Via. - Srivatsa Rangachar Srinivasa; Karthik Mohan; Wei-Hao Chen; Kuo-Hsinag Hsu; Xueqing Li 002; Meng-Fan Chang; Sumeet Kumar Gupta; John Sampson; Vijaykrishnan Narayanan (ISVLSI, 2017)

Incidental computing on IoT nonvolatile processors. - Kaisheng Ma; Xueqing Li 002; Jinyang Li 002; Yongpan Liu; Yuan Xie 001; Jack Sampson; Mahmut Taylan Kandemir; Vijaykrishnan Narayanan (MICRO, 2017)

Advancing Nonvolatile Computing With Nonvolatile NCFET Latches and Flip-Flops. - Xueqing Li 002; Sumitha George; Kaisheng Ma; Wei-Yu Tsai; Ahmedullah Aziz; John Sampson; Sumeet Kumar Gupta; Meng-Fan Chang; Yongpan Liu; Suman Datta; Vijaykrishnan Narayanan (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Maximum Energy Efficiency Tracking Circuits for Converter-Less Energy Harvesting Sensor Nodes. - Yinan Sun; Zhe Yuan; Yongpan Liu; Xueqing Li 002; Yu Wang 002; Qi Wei 001; Yiqun Wang; Vijaykrishnan Narayanan; Huazhong Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Dynamic Power and Energy Management for Energy Harvesting Nonvolatile Processor Systems. - Kaisheng Ma; Xueqing Li 002; Huichu Liu; Xiao Sheng; Yiqun Wang; Karthik Swaminathan; Yongpan Liu; Yuan Xie 001; John Sampson; Vijaykrishnan Narayanan (ACM Trans. Embed. Comput. Syst., 2017)

NEOFog: Nonvolatility-Exploiting Optimizations for Fog Computing. - Kaisheng Ma; Xueqing Li 002; Mahmut Taylan Kandemir; Jack Sampson; Vijaykrishnan Narayanan; Jinyang Li 002; Tongda Wu; Zhibo Wang 004; Yongpan Liu; Yuan Xie 001 (ASPLOS, 2018)

A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support. - Srivatsa Rangachar Srinivasa; Akshay Krishna Ramanathan; Xueqing Li 002; Wei-Hao Chen; Fu-Kuo Hsueh; Chih-Chao Yang; Chang-Hong Shen; Jia-Min Shieh; Sumeet Kumar Gupta; Meng-Fan Marvin Chang; Swaroop Ghosh; Jack Sampson; et al. (ISLPED, 2018)

Sticker: A 0.41-62.1 TOPS/W 8Bit Neural Network Processor with Multi-Sparsity Compatible Convolution Arrays and Online Tuning Acceleration for Fully Connected Layers. - Zhe Yuan; Jinshan Yue; Huanrui Yang; Zhibo Wang 004; Jinyang Li 002; Yixiong Yang; Qingwei Guo; Xueqing Li 002; Meng-Fan Chang; Huazhong Yang; Yongpan Liu (VLSI Circuits, 2018)

Redundancy-bandwidth scalable techniques for signal-independent element transition rates in high-speed current-steering DACs. - Longqiang Lai; Xueqing Li 002; Huazhong Yang (Int. J. Circuit Theory Appl., 2018)

An Accuracy Tunable Non-Boolean Co-Processor Using Coupled Nano-Oscillators. - Neel Gala; Sarada Krithivasan; Wei-Yu Tsai; Xueqing Li 002; Vijaykrishnan Narayanan; V. Kamakoti 001 (ACM J. Emerg. Technol. Comput. Syst., 2018)

IAA: Incidental Approximate Architectures for Extremely Energy-Constrained Energy Harvesting Scenarios using IoT Nonvolatile Processors. - Kaisheng Ma; Jinyang Li 002; Xueqing Li 002; Yongpan Liu; Yuan Xie 001; Mahmut T. Kandemir; Jack Sampson; Vijaykrishnan Narayanan (IEEE Micro, 2018)

Symmetric 2-D-Memory Access to Multidimensional Data. - Sumitha George; Xueqing Li 002; Minli Julie Liao; Kaisheng Ma; Srivatsa Rangachar Srinivasa; Karthik Mohan; Ahmedullah Aziz; John Sampson; Sumeet Kumar Gupta; Vijaykrishnan Narayanan (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Compact 3-D-SRAM Memory With Concurrent Row and Column Data Access Capability Using Sequential Monolithic 3-D Integration. - Srivatsa Rangachar Srinivasa; Xueqing Li 002; Meng-Fan Chang; John Sampson; Sumeet Kumar Gupta; Vijaykrishnan Narayanan (IEEE Trans. Very Large Scale Integr. Syst., 2018)

AERIS: area/energy-efficient 1T2R ReRAM based processing-in-memory neural network system-on-a-chip. - Jinshan Yue; Yongpan Liu; Fang Su; Shuangchen Li; Zhe Yuan; Zhibo Wang 004; Wenyu Sun; Xueqing Li 002; Huazhong Yang (ASP-DAC, 2019)

A Sparse-Adaptive CNN Processor with Area/Performance balanced N-Way Set-Associate PE Arrays Assisted by a Collision-Aware Scheduler. - Zhe Yuan; Jingyu Wang 004; Yixiong Yang; Jinshan Yue; Zhibo Wang 004; Xiaoyu Feng; Yanzhi Wang; Xueqing Li 002; Huazhong Yang; Yongpan Liu (A-SSCC, 2019)

A 3T/Cell Practical Embedded Nonvolatile Memory Supporting Symmetric Read and Write Access Based on Ferroelectric FETs. - Juejian Wu; Hongtao Zhong; Kai Ni 004; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (DAC, 2019)

A 16b Clockless Digital-to-Analog Converter with Ultra-Low-Cost Poly Resistors Supporting Wide-Temperature Range from -40°C to 85°C. - Xuedi Wang; Xueqing Li 002; Longqiang Lai; Huazhong Yang (ACM Great Lakes Symposium on VLSI, 2019)

A 65nm 0.39-to-140.3TOPS/W 1-to-12b Unified Neural Network Processor Using Block-Circulant-Enabled Transpose-Domain Acceleration with 8.1 × Higher TOPS/mm2and 6T HBST-TRAM-Based 2D Data-Reuse Architecture. - Jinshan Yue; Ruoyang Liu; Wenyu Sun; Zhe Yuan; Zhibo Wang 004; Yung-Ning Tu; Yi-Ju Chen; Ao Ren; Yanzhi Wang; Meng-Fan Chang; Xueqing Li 002; Huazhong Yang; et al. (ISSCC, 2019)

A 1.8mW Perception Chip with Near-Sensor Processing Scheme for Low-Power AIoT Applications. - Zheyu Liu; Erxiang Ren; Li Luo; Qi Wei 001; Xing Wu 005; Xueqing Li 002; Fei Qiao; Xin-Jun Liu; Huazhong Yang (ISVLSI, 2019)

Enabling New Computing Paradigms with Emerging Symmetric-Access Memories. - Juejian Wu; Mingyang Gu; Hongtao Zhong; Yunsong Tao; Fei Qiao; Huazhong Yang; Xueqing Li 002 (NANOARCH, 2019)

Design of 2T/Cell and 3T/Cell Nonvolatile Memories with Emerging Ferroelectric FETs. - Xueqing Li 002; Juejian Wu; Kai Ni 004; Sumitha George; Kaisheng Ma; John Sampson; Sumeet Kumar Gupta; Yongpan Liu; Huazhong Yang; Suman Datta; Vijaykrishnan Narayanan (IEEE Des. Test, 2019)

Emerging technologies and computing paradigms for the Internet of Everything applications. International Journal of Circuit, Theory, and Applications. - Aida Todri-Sanial; Xueqing Li 002; Juan Núñez 002 (Int. J. Circuit Theory Appl., 2019)

A 130-nm Ferroelectric Nonvolatile System-on-Chip With Direct Peripheral Restore Architecture for Transient Computing System. - Yongpan Liu; Fang Su; Yixiong Yang; Zhibo Wang 004; Yiqun Wang; Zewei Li; Xueqing Li 002; Ryuji Yoshimura; Takashi Naiki; Takashi Tsuwa; Takahiko Saito; Zhongjun Wang; et al. (IEEE J. Solid State Circuits, 2019)

Demystifying and Mitigating Code-Dependent Switching Distortions in Current-Steering DACs. - Longqiang Lai; Xueqing Li 002; Yushen Fu; Yongpan Liu; Huazhong Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

ROBIN: Monolithic-3D SRAM for Enhanced Robustness with In-Memory Computation Support. - Srivatsa Rangachar Srinivasa; Akshay Krishna Ramanathan; Xueqing Li 002; Wei-Hao Chen; Sumeet Kumar Gupta; Meng-Fan Chang; Swaroop Ghosh; Jack Sampson; Vijaykrishnan Narayanan (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Utilization of Negative-Capacitance FETs to Boost Analog Circuit Performances. - Yuhua Liang; Zhangming Zhu; Xueqing Li 002; Sumeet Kumar Gupta; Suman Datta; Vijaykrishnan Narayanan (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Adaptive Circuit Approaches to Low-Power Multi-Level/Cell FeFET Memory. - Juejian Wu; Yixin Xu 001; Bowen Xue; Yu Wang 002; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (ASP-DAC, 2020)

High PE Utilization CNN Accelerator with Channel Fusion Supporting Pattern-Compressed Sparse Neural Networks. - Jingyu Wang 004; Songming Yu; Jinshan Yue; Zhe Yuan; Zhuqing Yuan; Huazhong Yang; Xueqing Li 002; Yongpan Liu (DAC, 2020)

Design of Almost-Nonvolatile Embedded DRAM Using Nanoelectromechanical Relay Devices. - Hongtao Zhong; Mingyang Gu; Juejian Wu; Huazhong Yang; Xueqing Li 002 (DATE, 2020)

Design Insights of Non-volatile Processors and Accelerators in Energy Harvesting Systems. - Keni Qiu; Mengying Zhao; Zhenge Jia; Jingtong Hu; Chun Jason Xue; Kaisheng Ma; Xueqing Li 002; Yongpan Liu; Vijaykrishnan Narayanan (ACM Great Lakes Symposium on VLSI, 2020)

FeFET-based low-power bitwise logic-in-memory with direct write-back and data-adaptive dynamic sensing interface. - Mingyen Lee; Wenjun Tang; Bowen Xue; Juejian Wu; Mingyuan Ma; Yu Wang 002; Yongpan Liu; Deliang Fan; Vijaykrishnan Narayanan; Huazhong Yang; Xueqing Li 002 (ISLPED, 2020)

Integrated CAM-RAM Functionality using Ferroelectric FETs. - Sumitha George; Nicholas Jao; Akshay Krishna Ramanathan; Xueqing Li 002; Sumeet Kumar Gupta; John Sampson; Vijaykrishnan Narayanan (ISQED, 2020)

14.2 A 65nm 24.7µJ/Frame 12.3mW Activation-Similarity-Aware Convolutional Neural Network Video Processor Using Hybrid Precision, Inter-Frame Data Reuse and Mixed-Bit-Width Difference-Frame Data Codec. - Zhe Yuan; Yixiong Yang; Jinshan Yue; Ruoyang Liu; Xiaoyu Feng; Zhiting Lin; Xiulong Wu; Xueqing Li 002; Huazhong Yang; Yongpan Liu (ISSCC, 2020)

14.3 A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse. - Jinshan Yue; Zhe Yuan; Xiaoyu Feng; Yifan He 003; Zhixiao Zhang; Xin Si; Ruhui Liu; Meng-Fan Chang; Xueqing Li 002; Huazhong Yang; Yongpan Liu (ISSCC, 2020)

High Area/Energy Efficiency RRAM CNN Accelerator with Kernel-Reordering Weight Mapping Scheme Based on Pattern Pruning. - Songming Yu; Yongpan Liu; Lu Zhang; Jingyu Wang 004; Jinshan Yue; Zhuqing Yuan; Xueqing Li 002; Huazhong Yang (CoRR, 2020)

STICKER: An Energy-Efficient Multi-Sparsity Compatible Accelerator for Convolutional Neural Networks in 65-nm CMOS. - Zhe Yuan; Yongpan Liu; Jinshan Yue; Yixiong Yang; Jingyu Wang 004; Xiaoyu Feng; Jian Zhao 004; Xueqing Li 002; Huazhong Yang (IEEE J. Solid State Circuits, 2020)

One-Shot Refresh: A Low-Power Low-Congestion Approach for Dynamic Memories. - Hongtao Zhong; Mingyang Gu; Yu Wang 002; Yongpan Liu; Vijaykrishnan Narayanan; Huazhong Yang; Xueqing Li 002 (IEEE Trans. Circuits Syst., 2020)

Dynamic Ternary Content-Addressable Memory Is Indeed Promising: Design and Benchmarking Using Nanoelectromechanical Relays. - Hongtao Zhong; Shengjie Cao; Huazhong Yang; Xueqing Li 002 (DATE, 2021)

A 16-Bit 4.0-GS/s Calibration-Free 65nm DAC with >70dBc SFDR and <-80dBc IM3 up to 1GHz Using Constant-Activity Element Switching. - Chengyu Huang 001; Yushen Fu; Zekun Yang; Yang Liu; Nan Sun 001; Xueqing Li 002; Huazhong Yang (ESSCIRC, 2021)

Exploiting FeFET Switching Stochasticity for Low-Power Reconfigurable Physical Unclonable Function. - Xinrui Guo; Xiaoyang Ma; Franz Müller 001; Ricardo Olivo; Juejian Wu; Kai Ni 004; Thomas Kämpfe; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (ESSDERC, 2021)

Capacitive Content-Addressable Memory: A Highly Reliable and Scalable Approach to Energy-Efficient Parallel Pattern Matching Applications. - Nuo Xiu; Yiming Chen; Guodong Yin; Xiaoyang Ma; Huazhong Yang; Sumitha George; Xueqing Li 002 (ACM Great Lakes Symposium on VLSI, 2021)

Dynamic Switching Sequence to Compensate the Integral Nonlinearity in Current-Steering DACs. - Yang Liu; Yushen Fu; Chengyu Huang 001; Huazhong Yang; Xueqing Li 002 (ISCAS, 2021)

Almost-Nonvolatile IGZO-TFT-Based Near-Sensor In-Memory Computing. - Jialong Liu; Wenjun Tang; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (ISCAS, 2021)

Reducing Signal Swing Overheads to Only 8% in Background 3rd-Order Inter-Stage Gain Error Calibration for Pipeline ADCs. - Zekun Yang; Pei Yang; Xiumei Yin; Xueqing Li 002; Huazhong Yang (ISCAS, 2021)

A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating. - Jinshan Yue; Xiaoyu Feng; Yifan He 003; Yuxuan Huang; Yipeng Wang 009; Zhe Yuan; Mingtao Zhan; Jiaxin Liu; Jian-Wei Su; Yen-Lin Chung; Ping-Chun Wu; Li-Yang Hung; et al. (ISSCC, 2021)

High Area/Energy Efficiency RRAM CNN Accelerator with Pattern-Pruning-Based Weight Mapping Scheme. - Songming Yu; Lu Zhang; Jingyu Wang 004; Jinshan Yue; Zhuqing Yuan; Xueqing Li 002; Huazhong Yang; Yongpan Liu (NVMSA, 2021)

STICKER-T: An Energy-Efficient Neural Network Processor Using Block-Circulant Algorithm and Unified Frequency-Domain Acceleration. - Jinshan Yue; Yongpan Liu; Ruoyang Liu; Wenyu Sun; Zhe Yuan; Yung-Ning Tu; Yi-Ju Chen; Ao Ren; Yanzhi Wang; Meng-Fan Chang; Xueqing Li 002; Huazhong Yang (IEEE J. Solid State Circuits, 2021)

Enabling Lower-Power Charge-Domain Nonvolatile In-Memory Computing With Ferroelectric FETs. - Guodong Yin; Yi Cai 003; Juejian Wu; Zhengyang Duan; Zhenhua Zhu; Yongpan Liu; Yu Wang 002; Huazhong Yang; Xueqing Li 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

DyTAN: Dynamic Ternary Content Addressable Memory Using Nanoelectromechanical Relays. - Hongtao Zhong; Shengjie Cao; Li Jiang 002; Xia An; Vijaykrishnan Narayanan; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (IEEE Trans. Very Large Scale Integr. Syst., 2021)

YOLoC: deploy large-scale neural network by ROM-based computing-in-memory using residual branch on a chip. - Yiming Chen; Guodong Yin; Zhanhong Tan; Mingyen Lee; Zekun Yang; Yongpan Liu; Huazhong Yang; Kaisheng Ma; Xueqing Li 002 (DAC, 2022)

CREAM: computing in ReRAM-assisted energy and area-efficient SRAM for neural network acceleration. - Liukai Xu; Songyuan Liu; Zhi Li 058; Dengfeng Wang; Yiming Chen; Yanan Sun 003; Xueqing Li 002; Weifeng He; Shi Xu (DAC, 2022)

Hidden-ROM: A Compute-in-ROM Architecture to Deploy Large-Scale Neural Networks on Chip with Flexible and Scalable Post-Fabrication Task Transfer Capability. - Yiming Chen; Guodong Yin; Mingyen Lee; Wenjun Tang; Zekun Yang; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (ICCAD, 2022)

An 8T/Cell FeFET-Based Nonvolatile SRAM with Improved Density and Sub-fJ Backup and Restore Energy. - Jianfeng Wang; Nuo Xiu; Juejian Wu; Yiming Chen; Yanan Sun 003; Huazhong Yang; Vijaykrishnan Narayanan; Sumitha George; Xueqing Li 002 (ISCAS, 2022)

FAST: A Fully-Concurrent Access Technique to All SRAM Rows for Enhanced Speed and Energy Efficiency in Data-Intensive Applications. - Yiming Chen; Yushen Fu; Mingyen Lee; Sumitha George; Yongpan Liu; Vijaykrishnan Narayanan; Huazhong Yang; Xueqing Li 002 (CoRR, 2022)

ALL-MASK: A Reconfigurable Logic Locking Method for Multicore Architecture with Sequential-Instruction-Oriented Key. - Jianfeng Wang; Zhonghao Chen; Jiahao Zhang; Yixin Xu 001; Tongguang Yu; Enze Ye; Ziheng Zheng; Huazhong Yang; Sumitha George; Yongpan Liu; Vijaykrishnan Narayanan; Xueqing Li 002 (CoRR, 2022)

GRAPHIC: GatheR-And-Process in Highly parallel with In-SSD Compression Architecture in Very Large-Scale Graph. - Yiming Chen; Guohao Dai; Mufeng Zhou; Mingyen Lee; Nagadastagiri Challapalle; Guodong Yin; Zekun Yang; Yongpan Liu; Huazhong Yang; Vijaykrishnan Narayanan; Xueqing Li 002 (CoRR, 2022)

Ferroelectric FET-based strong physical unclonable function: a low-power, high-reliable and reconfigurable solution for Internet-of-Things security. - Xinrui Guo; Xiaoyang Ma; Franz Müller 001; Kai Ni 004; Thomas Kämpfe; Yongpan Liu; Vijaykrishnan Narayanan; Xueqing Li 002 (CoRR, 2022)

A 65nm 8b-Activation 8b-Weight SRAM-Based Charge-Domain Computing-in-Memory Macro Using A Fully-Parallel Analog Adder Network and A Single-ADC Interface. - Guodong Yin; Mufeng Zhou; Yiming Chen; Wenjun Tang; Zekun Yang; Mingyen Lee; Xirui Du; Jinshan Yue; Jiaxin Liu; Huazhong Yang; Yongpan Liu; Xueqing Li 002 (CoRR, 2022)

Eliminating Leakage in Volatile Memory with Anti-Ferroelectric Transistors. - Hongtao Zhong; Zijie Zheng; Kai Ni 004; Xiao Gong; Huazhong Yang; Xueqing Li 002 (CoRR, 2022)

A 65-nm Energy-Efficient Interframe Data Reuse Neural Network Accelerator for Video Applications. - Yixiong Yang; Yongpan Liu; Zhe Yuan; Wenyu Sun; Ruoyang Liu; Jingyu Wang 004; Jinshan Yue; Xiaoyu Feng; Zhuqing Yuan; Xueqing Li 002; Huazhong Yang (IEEE J. Solid State Circuits, 2022)

STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse. - Jinshan Yue; Yongpan Liu; Zhe Yuan; Xiaoyu Feng; Yifan He 002; Wenyu Sun; Zhixiao Zhang; Xin Si; Ruhui Liu; Zi Wang; Meng-Fan Chang; Chunmeng Dou; et al. (IEEE J. Solid State Circuits, 2022)

PACA: A Pattern Pruning Algorithm and Channel-Fused High PE Utilization Accelerator for CNNs. - Jingyu Wang 004; Songming Yu; Zhuqing Yuan; Jinshan Yue; Zhe Yuan; Ruoyang Liu; Yanzhi Wang; Huazhong Yang; Xueqing Li 002; Yongpan Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

CapCAM: A Multilevel Capacitive Content Addressable Memory for High-Accuracy and High-Scalability Search and Compute Applications. - Xiaoyang Ma; Hongtao Zhong; Nuo Xiu; Yiming Chen; Guodong Yin; Vijaykrishnan Narayanan; Yongpan Liu; Kai Ni 004; Huazhong Yang; Xueqing Li 002 (IEEE Trans. Very Large Scale Integr. Syst., 2022)

WeightLock: A Mixed-Grained Weight Encryption Approach Using Local Decrypting Units for Ciphertext Computing in DNN Accelerators. - Jianfeng Wang; Zhonghao Chen; Yiming Chen; Yixin Xu 001; Tianyi Wang; Yao Yu; Vijaykrishnan Narayanan; Sumitha George; Huazhong Yang; Xueqing Li 002 (AICAS, 2023)

A 10TFLOPS Datacenter-Oriented GPU with 4-Corner Stacked 64GB Memory by The Means of 2.5D Packaging Technology. - Shuang Wang; Weiliang Chen; Xueqing Li 002; Leibo Liu; Huazhong Yang (A-SSCC, 2023)

Victor: A Variation-resilient Approach Using Cell-Clustered Charge-domain computing for High-density High-throughput MLC CiM. - Mingyen Lee; Wenjun Tang; Yiming Chen; Juejian Wu; Hongtao Zhong; Yixin Xu 001; Yongpan Liu; Huazhong Yang; Vijaykrishnan Narayanan; Xueqing Li 002 (DAC, 2023)

ASMCap: An Approximate String Matching Accelerator for Genome Sequence Analysis Based on Capacitive Content Addressable Memory. - Hongtao Zhong; Zhonghao Chen; Wenqin Huangfu; Chen Wang; Yixin Xu 001; Tianyi Wang; Yao Yu; Yongpan Liu; Vijaykrishnan Narayanan; Huazhong Yang; Xueqing Li 002 (DAC, 2023)

TL-nvSRAM-CIM: Ultra-High-Density Three-Level ReRAM-Assisted Computing-in-nvSRAM with DC-Power Free Restore and Ternary MAC Operations. - Dengfeng Wang; Liukai Xu; Songyuan Liu; Zhi Li 058; Yiming Chen; Weifeng He; Xueqing Li 002; Yanan Sun 003 (ICCAD, 2023)

Lowering Latency of Embedded Memory by Exploiting In-Cell Victim Cache Hierarchy Based on Emerging Multi-Level Memory Devices. - Juejian Wu; Tianyu Liao; Taixin Li; Yixin Xu 001; Vijaykrishnan Narayanan; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (ICCAD, 2023)

A 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference. - Yifan He 003; Haikang Diao; Chen Tang; Wenbin Jia; Xiyuan Tang; Yuan Wang 001; Jinshan Yue; Xueqing Li 002; Huazhong Yang; Hongyang Jia; Yongpan Liu (ISSCC, 2023)

A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse-Digital Architecture. - Jinshan Yue; Chaojie He; Zi Wang; Zhaori Cong; Yifan He 002; Mufeng Zhou; Wenyu Sun; Xueqing Li 002; Chunmeng Dou; Feng Zhang 014; Huazhong Yang; Yongpan Liu; et al. (ISSCC, 2023)

Design Exploration of Dynamic Multi-Level Ternary Content-Addressable Memory Using Nanoelectromechanical Relays. - Taixin Li; Hongtao Zhong; Sumitha George; Vijaykrishnan Narayanan; Liang Shi 001; Huazhong Yang; Xueqing Li 002 (ISVLSI, 2023)

Fe-GCN: A 3D FeFET Memory Based PIM Accelerator for Graph Convolutional Networks. - Hongtao Zhong; Yu Zhu; Longfei Luo; Taixin Li; Chen Wang; Yixin Xu 001; Tianyi Wang; Yao Yu; Vijaykrishnan Narayanan; Yongpan Liu; Liang Shi 001; Huazhong Yang; et al. (ISVLSI, 2023)

A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro. - Jinshan Yue; Mingtao Zhan; Zi Wang; Yifan He 002; Yaolei Li; Songming Yu; Wenyu Sun; Lu Jie 001; Chunmeng Dou; Xueqing Li 002; Nan Sun 001; Huazhong Yang; et al. (VLSI Technology and Circuits, 2023)

CREAM: Computing in ReRAM-Assisted Energy- and Area-Efficient SRAM for Reliable Neural Network Acceleration. - Yanan Sun 003; Dengfeng Wang; Liukai Xu; Yiming Chen; Zhi Li 058; Songyuan Liu; Weifeng He; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

FeFET-Based Logic-in-Memory Supporting SA-Free Write-Back and Fully Dynamic Access With Reduced Bitline Charging Activity and Recycled Bitline Charge. - Wenjun Tang; Mingyen Lee; Juejian Wu; Yixin Xu 001; Yao Yu; Yongpan Liu; Kai Ni 004; Yu Wang 002; Huazhong Yang; Vijaykrishnan Narayanan; Xueqing Li 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 6.0-GS/s Time-Interleaved DAC Using an Asymmetric Current-Tree Summation Network and Differential Clock Timing Calibration. - Yushen Fu; Chengyu Huang 001; Limeng Sun; Weiguang Meng; Xueqing Li 002; Huazhong Yang (IEEE Trans. Very Large Scale Integr. Syst., 2023)

FAST: A Fully-Concurrent Access SRAM Topology for High Row-Wise Parallelism Applications Based on Dynamic Shift Operations. - Yiming Chen; Yushen Fu; Mingyen Lee; Sumitha George; Yongpan Liu; Vijaykrishnan Narayanan; Huazhong Yang; Xueqing Li 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 16-Bit 4.0-GS/s Calibration-Free 65 nm DAC Achieving >70 dBc SFDR and < -80 dBc IM3 Up to 1 GHz With Enhanced Constant-Switching-Activity Data-Weighted-Averaging. - Yushen Fu; Chengyu Huang 001; Longqiang Lai; Nan Sun 001; Xueqing Li 002; Huazhong Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

SAMBA: Single-ADC Multi-Bit Accumulation Compute-in-Memory Using Nonlinearity- Compensated Fully Parallel Analog Adder Tree. - Yiming Chen; Guodong Yin; Mufeng Zhou; Wenjun Tang; Zekun Yang; Mingyen Lee; Xirui Du; Jinshan Yue; Jiaxin Liu; Huazhong Yang; Yongpan Liu; Xueqing Li 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Low-Power and Scalable BEOL-Compatible IGZO TFT eDRAM-Based Charge-Domain Computing. - Wenjun Tang; Jialong Liu; Chen Sun 010; Zijie Zheng; Yongpan Liu; Huazhong Yang; Chen Jiang; Kai Ni 004; Xiao Gong; Xueqing Li 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

ZEBRA: A Zero-Bit Robust-Accumulation Compute-In-Memory Approach for Neural Network Acceleration Utilizing Different Bitwise Patterns. - Yiming Chen; Guodong Yin; Hongtao Zhong; Mingyen Lee; Huazhong Yang; Sumitha George; Vijaykrishnan Narayanan; Xueqing Li 002 (ASPDAC, 2024)

A 28nm 166.9 TOPS/W x Mb/mm2 DRAM-Free QLC Compute-in-ROM Macro Supporting High Task-Level Inference Energy Efficiency for Tiny AI Edge Devices. - Ling-An Cheong; Chen Wang; Mufeng Zhou; Tianyu Liao; Mingyen Lee; Yue Ke; Wenjun Tang; Yiming Chen; Xirui Du; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (A-SSCC, 2024)

CiMSAT: Exploiting SAT Analysis to Attack Compute-in-Memory Architecture Defenses. - Jianfeng Wang; Huazhong Yang; Shuwen Deng; Xueqing Li 002 (CCS, 2024)

A 16-bit 10-GS/s Calibration-Free DAC Achieving <-77dBc IM3 up to 4.95GHz in 28nm CMOS. - Chengyu Huang 001; Kezhuo Ma; Sihao Chen; Jiaxuan Fan; Nan Sun 001; Huazhong Yang; Xueqing Li 002 (CICC, 2024)

A 28nm 8928Kb/mm2-Weight-Density Hybrid SRAM/ROM Compute-in-Memory Architecture Reducing >95% Weight Loading from DRAM. - Guodong Yin; Yiming Chen; Mingyen Lee; Xirui Du; Yue Ke; Wenjun Tang; Zhonghao Chen; Mufeng Zhou; Jinshan Yue; Huazhong Yang; Hongyang Jia; Yongpan Liu; et al. (CICC, 2024)

Cross-Layer Exploration and Chip Demonstration of In-Sensor Computing for Large-Area Applications with Differential-Frame ROM-Based Compute-In-Memory. - Jialong Liu; Wenjun Tang; Deyun Chen; Chen Jiang; Huazhong Yang; Xueqing Li 002 (DAC, 2024)

HEIRS: Hybrid Three-Dimension RRAM- and SRAM-CIM Architecture for Multi-task Transformer Acceleration. - Liukai Xu; Shuai Yuan 016; Dengfeng Wang; Yiming Chen; Xueqing Li 002; Yanan Sun 003 (DAC, 2024)

CafeHD: A Charge-Domain FeFET-Based Compute-in-Memory Hyperdimensional Encoder with Hypervector Merging. - Taixin Li; Hongtao Zhong; Juejian Wu; Thomas Kämpfe; Kai Ni 004; Vijaykrishnan Narayanan; Huazhong Yang; Xueqing Li 002 (DATE, 2024)

TroScan: Enhancing On-Chip Delivery Resilience to Physical Attack Through Frequency-Triggered Key Generation. - Jianfeng Wang; Shuwen Deng; Huazhong Yang; Vijaykrishnan Narayanan; Xueqing Li 002 (DATE, 2024)

REMNA: Variation-Resilient and Energy-Efficient MLC FeFET Computing-in-Memory Using NAND Flash-Like Read and Adaptive Control. - Taixin Li; Hongtao Zhong; Yixin Xu 001; Vijaykrishnan Narayanan; Kai Ni 004; Huazhong Yang; Thomas Kämpfe; Xueqing Li 002 (ICCAD, 2024)

NAND-Tree: A 3D NAND Flash Based Processing In Memory Accelerator for Tree-Based Models on Large-Scale Tabular Data. - Hongtao Zhong; Taixin Li; Yiming Chen; Wenjun Tang; Juejian Wu; Huazhong Yang; Xueqing Li 002 (ICCAD, 2024)

A 1024-Channel Neurostimulation System Enabled by Photolithographic Organic Thin-Film Transistors with High Uniformity. - Bowen Liu; Yangkun Hou; Yueshan Qin; Jiwei Zou; Hanbin Ma; Yongpan Liu; Huazhong Yang; Xueqing Li 002; Chen Jiang (ISCAS, 2024)

34.7 A 28nm 2.4Mb/mm2 6.9 - 16.3TOPS/mm2 eDRAM-LUT-Based Digital-Computing-in-Memory Macro with In-Memory Encoding and Refreshing. - Yifan He 003; Shupei Fan; Xuan Li; Luchang Lei; Wenbin Jia; Chen Tang; Yaolei Li; Zongle Huang; Zhike Du; Jinshan Yue; Xueqing Li 002; Huazhong Yang; et al. (ISSCC, 2024)

GRAPHIC: Gather and Process Harmoniously in the Cache With High Parallelism and Flexibility. - Yiming Chen; Mingyen Lee; Guohao Dai; Mufeng Zhou; Nagadastagiri Challapalle; Tianyi Wang; Yao Yu; Yongpan Liu; Yu Wang 002; Huazhong Yang; Vijaykrishnan Narayanan; Xueqing Li 002 (IEEE Trans. Emerg. Top. Comput., 2024)

ProtFe: Low-Cost Secure Power Side-Channel Protection for General and Custom FeFET-Based Memories. - Taixin Li; Boran Sun; Hongtao Zhong; Yixin Xu 001; Vijaykrishnan Narayanan; Liang Shi 001; Tianyi Wang; Yao Yu; Thomas Kämpfe; Kai Ni 004; Huazhong Yang; Xueqing Li 002 (ACM Trans. Design Autom. Electr. Syst., 2024)

TFT-Based Near-Sensor In-Memory Computing: Circuits and Architecture Perspectives of Large-Area eDRAM and ROM CiM Chips. - Jialong Liu; Wenjun Tang; Hongtian Li; Deyun Chen; Weihang Long; Yongpan Liu; Chen Jiang; Huazhong Yang; Xueqing Li 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

ULSeq-TA: Ultra-Long Sequence Attention Fusion Transformer Accelerator Supporting Grouped Sparse Softmax and Dual-Path Sparse LayerNorm. - Jingyu Wang 004; Lu Zhang; Xueqing Li 002; Huazhong Yang; Yongpan Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

A Module-Level Configuration Methodology for Programmable Camouflaged Logic. - Jianfeng Wang; Zhonghao Chen; Jiahao Zhang; Yixin Xu 001; Tongguang Yu; Ziheng Zheng; Enze Ye; Sumitha George; Huazhong Yang; Yongpan Liu; Kai Ni 004; Vijaykrishnan Narayanan; et al. (ACM Trans. Design Autom. Electr. Syst., 2024)

An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong Weight Update. - Jinshan Yue; Yongpan Liu; Xiaoyu Feng; Yifan He 002; Jingyu Wang 004; Zhe Yuan; Mingtao Zhan; Jiaxin Liu; Jian-Wei Su; Yen-Lin Chung; Ping-Chun Wu; Li-Yang Hong; et al. (IEEE J. Solid State Circuits, 2024)

Cramming More Weight Data Onto Compute-in-Memory Macros for High Task-Level Energy Efficiency Using Custom ROM With 3984-kb/mm2 Density in 65-nm CMOS. - Guodong Yin; Yiming Chen; Mufeng Zhou; Wenjun Tang; Mingyen Lee; Zekun Yang; Tianyu Liao; Xirui Du; Vijaykrishnan Narayanan; Huazhong Yang; Hongyang Jia; Yongpan Liu; et al. (IEEE J. Solid State Circuits, 2024)

A 28-nm Floating-Point Computing-in-Memory Processor Using Intensive-CIM Sparse-Digital Architecture. - Shengzhe Yan; Jinshan Yue; Chaojie He; Zi Wang; Zhaori Cong; Yifan He 002; Mufeng Zhou; Wenyu Sun; Xueqing Li 002; Chunmeng Dou; Feng Zhang 014; Huazhong Yang; et al. (IEEE J. Solid State Circuits, 2024)

3D-METRO: Deploy Large-Scale Transformer Model on A Chip Using Transistor-Less 3D-Metal-ROM-Based Compute-in-Memory Macro. - Yiming Chen; Xirui Du; Guodong Yin; Wenjun Tang; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (ASP-DAC, 2025)

DCiROM: A Fully Digital Compute-in-ROM Design Approach to High Energy Efficiency of DNN Inference at Task Level. - Tianyi Yu; Tianyu Liao; Mufeng Zhou; Xiaotian Chu; Guodong Yin; Mingyen Lee; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (ASP-DAC, 2025)

Pro-Cache-CIM: A 28nm 69.4TOPS/W Product-Cache-based Digital-Compute-in-Memory Macro Leveraging Data Locality Pattern in Vision AI Tasks. - Wenbin Jia; Yifan He 003; Xiang Li; Yixuan Xie; Zongle Huang; Wenxun Wang; Boju Chen; Yaolei Li; Jinshan Yue; Xueqing Li 002; Huazhong Yang; Hongyang Jia; et al. (CICC, 2025)

DSC-ROM: A Fully Digital Sparsity-Compressed Compute-in-ROM Architecture for on-Chip Deployment of Large-Scale DNNs. - Tianyi Yu; Zhonghao Chen; Yiming Chen; Shuang Wang; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (DATE, 2025)

ADDR: Architecture Design and Model Deployment Optimization for Hybrid SRAM-ROM Compute-in-Memory. - Teng Wan; Yiming Chen; Zekai Chen; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (ACM Great Lakes Symposium on VLSI, 2025)

Kung-Fu: An Energy-Efficient Compute-In-Memory Approach for Neural Network Inference Using Multi-Level Binary Computing Fusion. - Tianyu Liao; Yiming Chen; Wenjun Tang; Zhonghao Chen; Yu Wang 002; Huazhong Yang; Xueqing Li 002 (ISCAS, 2025)

A Threshold-Voltage Compensation Circuit for Organic Thin-Film Transistor Active-Matrix Neurostimulation System. - Shikai Wang; Bowen Liu; Xueqing Li 002; Huazhong Yang; Yongpan Liu; Chen Jiang (ISCAS, 2025)

3D-Domino: Ultra-Dense High-Accuracy 3D eDRAM-ROM Compute-In-Memory Based on CAA-IGZO TFT for Edge Large-Scale Model Inference. - Zhuoya Wang; Wenjun Tang; Chen Jiang; Huazhong Yang; Vijaykrishnan Narayanan; Xueqing Li 002 (ISCAS, 2025)

A Multiply-Less Approximate SRAM Compute-In-Memory Macro for Neural-Network Inference. - Haikang Diao; Yifan He 003; Xuan Li; Chen Tang; Wenbin Jia; Jinshan Yue; Haoyang Luo; Jiahao Song; Xueqing Li 002; Huazhong Yang; Hongyang Jia; Yongpan Liu; et al. (IEEE J. Solid State Circuits, 2025)

A 28-nm 8-Bit 16-GS/ DAC With >60 dBc/>40 dBc SFDR Up To 2.3 GHz/5.4 GHz Using 4-Channel NRZ-Output-Overlapped Time-Interleaving. - Sihao Chen; Chengyu Huang 001; Limeng Sun; Yang Liu; Wenjun Tang; Jiaxuan Fan; Nan Sun 001; Yong Chen 005; Huazhong Yang; Xueqing Li 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)