A fast multi-core virtual platform and its application on software development. - Zongyan Wang; Dexue Zhang; Xueqiu Yu; Zhiyi Yu; Xiaoyang Zeng (ASICON, 2013)

A turbo decoder implementation for LTE downlink mapped on a multi-core processor platform. - Qing Zhang; Xueqiu Yu; Zhiyi Yu; Xiaoyang Zeng (ASICON, 2013)

A low power register file with asynchronously controlled read-isolation and software-directed write-discarding. - Zheng Yu 001; Jiajie Zhang; Xueqiu Yu; Xiaoyang Zeng; Zhiyi Yu (ISCAS, 2013)

A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array. - Peng Ou; Jiajie Zhang; Heng Quan; Yi Li; Maofei He; Zheng Yu 001; Xueqiu Yu; Shile Cui; Jie Feng; Shikai Zhu; Jie Lin; Ming-e Jing; et al. (ISSCC, 2013)

Low-Power Multicore Processor Design With Reconfigurable Same-Instruction Multiple Process. - Zheng Yu 001; Zhiyi Yu; Xueqiu Yu; Ningxi Liu; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2014)