A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs. - An Guo 001; Xin Si; Xi Chen 107; Fangyuan Dong; Xingyu Pu; Dongqi Li; Yongliang Zhou; Lizheng Ren; Yeyang Xue; Xueshan Dong; Hui Gao; Yiran Zhang; et al. (ISSCC, 2023)

A 28nm 128-kb Exponent- and Mantissa-Computation-InMemory Dual-macro for Floating-point and INT CNNs. - An Guo 001; Xueshan Dong; Fangyuan Dong; Dongqi Li; Yiran Zhang; Jingmin Zhang; Yuchen Tang; Yuhui Shi; Xiao Tan; Bo Liu 019; Weiwei Shan; Hao Cai 001; et al. (A-SSCC, 2024)

A 28-nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs. - An Guo 001; Chen Xi; Fangyuan Dong; Xingyu Pu; Dongqi Li; Jingmin Zhang; Xueshan Dong; Hui Gao; Yiran Zhang; Bo Wang 023; Jun Yang 006; Xin Si (IEEE J. Solid State Circuits, 2024)