A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency Divider. - Baoyong Chi; Xueyi Yu; Woogeun Rhee; Zhihua Wang 001 (ISCAS, 2007)

A 1GHz Fractional-N PLL Clock Generator with Low-OSR ΔΣ Modulation and FIR-Embedded Noise Filtering. - Xueyi Yu; Yuanfeng Sun; Li Zhang 023; Woogeun Rhee; Zhihua Wang 001 (ISSCC, 2008)

Customized Zero Frequency Control for Hybrid FIR Noise Filtering in SigmaDelta Fractional-N PLL. - Jian Qiao; Xueyi Yu; Woogeun Rhee; Zhihua Wang 001 (ISCAS, 2009)

A 0.4-to-1.6GHz low-OSR ΔΣ DLL with self-referenced multiphase generation. - Xueyi Yu; Woogeun Rhee; Zhihua Wang 001; Jung-Bae Lee; Changhyun Kim (ISSCC, 2009)

A Hybrid Spur Compensation Technique for Finite-Modulo Fractional-N Phase-Locked Loops. - Li Zhang 023; Xueyi Yu; Yuanfeng Sun; Woogeun Rhee; Dawn Wang; Zhihua Wang 001; Hongyi Chen (IEEE J. Solid State Circuits, 2009)

A ΔΣ Fractional-N Synthesizer With Customized Noise Shaping for WCDMA/HSDPA Applications. - Xueyi Yu; Yuanfeng Sun; Woogeun Rhee; Hyung Ki Ahn; Byeong-Ha Park; Zhihua Wang 001 (IEEE J. Solid State Circuits, 2009)

An FIR-Embedded Noise Filtering Method for ΔΣ Fractional-N PLL Clock Generators. - Xueyi Yu; Yuanfeng Sun; Woogeun Rhee; Zhihua Wang 001 (IEEE J. Solid State Circuits, 2009)

A Continuously Tunable Hybrid LC-VCO PLL With Mixed-Mode Dual-Path Control and Bi-level Delta-Sigma Modulated Coarse Tuning. - Yuanfeng Sun; Jian Qiao; Xueyi Yu; Woogeun Rhee; Byeong-Ha Park; Zhihua Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

A PLL/DLL based CDR with ΔΣ frequency tracking and low algorithmic jitter generation. - Shuli Geng; Ni Xu; Jun Li 024; Xueyi Yu; Woogeun Rhee; Zhihua Wang 001 (ISCAS, 2013)

A Fractional-N PLL With Space-Time Averaging for Quantization Noise Reduction. - Yanlong Zhang; Arindam Sanyal; Xueyi Yu; Xing Quan; Kailin Wen; Xiyuan Tang; Gang Jin; Li Geng; Nan Sun 001 (IEEE J. Solid State Circuits, 2020)