A Novel GALS Single-Track Protocol Asynchronous Communication Circuits. - Xuguang Guan; Duan Zhou; Dan Wang; Yintang Yang; Zhangming Zhu (PACCS, 2009)

A GALS Delay-insensitive Self-timed Wrapper for Network on Chips. - Xuguang Guan; Duan Zhou; Yintang Yang; Zhangming Zhu (PACCS, 2009)

Performance Analysis of Low Power Null Convention Logic Units with Power Cutoff. - Xuguang Guan; Yu Liu; Yintang Yang (APWCS, 2010)

An asynchronous low latency ordered arbiter for network on chips. - Yu Liu; Xuguang Guan; Yang Yang; Yintang Yang (ICNC, 2010)

High Speed Multi-Resource Arbiter with Active Virtual Channel Allocation for Network on Chips. - Xuguang Guan; Zhangming Zhu; Duan Zhou; Yintang Yang (J. Circuits Syst. Comput., 2010)

Asymmetric multiprocessing for motion control based on Zynq SoC. - Xinyu Chen; Yong Gu; Chenxu Wang; Xuguang Guan (FPT, 2016)

The configurable current flattening circuit for DPA countermeasures. - Yong Gu; Xuguang Guan; Tong Zhou (ASICON, 2017)

A new countermeasure against side channel attack for HMAC-SM3 hardware. - Jia-Wei Ma; Xuguang Guan; Tong Zhou; Tao Sun (ASICON, 2017)