Dyn-Bitpool: A Two-sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization. - Xujiang Xiang; Zhiheng Yue; Yuxuan Li; Liuxin Lv; Shaojun Wei; Yang Hu 001; Shouyi Yin (DAC, 2024)

15.1 A 0.795fJ/bit Physically-Unclonable Function-Protected TCAM for a Software-Defined Networking Switch. - Zhiheng Yue; Xujiang Xiang; Fengbin Tu; Yang Wang 089; Yiming Wang; Shaojun Wei; Yang Hu 001; Shouyi Yin (ISSCC, 2024)

14.4 A 51.6TFLOPs/W Full-Datapath CIM Macro Approaching Sparsity Bound and <-30 Loss for Compound AI. - Zhiheng Yue; Xujiang Xiang; Yang Wang 089; Ruiqi Guo; Huiming Han; Shaojun Wei; Yang Hu 001; Shouyi Yin (ISSCC, 2025)

Dyn-Bitpool: A 28 nm 27 TOPS/W Two-Sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization. - Xujiang Xiang; Zhiheng Yue; Xiaolong Zhang; Shaojun Wei; Yang Hu 001; Shouyi Yin (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)