FPGA-Accelerated Maze Routing Kernel for VLSI Designs. - Xun Jiang 002; Jiarui Wang; Yibo Lin; Zhongfeng Wang 001 (ASP-DAC, 2022)

General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism. - Zizheng Guo; Zuodong Zhang; Xun Jiang 002; Wuxi Li; Yibo Lin; Runsheng Wang; Ru Huang 001 (DAC, 2023)

Invited Paper: Accelerating Routability and Timing Optimization with Open-Source AI4EDA Dataset CircuitNet and Heterogeneous Platforms. - Xun Jiang 002; Zizheng Guo; Zhuomin Chai; Yuxiang Zhao; Yibo Lin; Runsheng Wang; Ru Huang 001 (ICCAD, 2023)

PowPrediCT: Cross-Stage Power Prediction with Circuit-Transformation-Aware Learning. - Yufan Du; Zizheng Guo; Xun Jiang 002; Zhuomin Chai; Yuxiang Zhao; Yibo Lin; Runsheng Wang; Ru Huang 001 (DAC, 2024)

Top-Level Routing for Multiply-Instantiated Blocks with Topology Hashing. - Jiarui Wang; Xun Jiang 002; Yibo Lin (DAC, 2024)

Oltron: Algorithm-Hardware Co-design for Outlier-Aware Quantization of LLMs with Inter-/Intra-Layer Adaptation. - Chenhao Xue; Chen Zhang 001; Xun Jiang 002; Zhutianya Gao; Yibo Lin; Guangyu Sun 003 (DAC, 2024)

CircuitNet 2.0: An Advanced Dataset for Promoting Machine Learning Innovations in Realistic Chip Design Environment. - Xun Jiang 002; Zhuomin Chai; Yuxiang Zhao; Yibo Lin; Runsheng Wang; Ru Huang 001 (ICLR, 2024)

First Experimental Demonstration of Self-Aligned Flip FET (FFET): A Breakthrough Stacked Transistor Technology with 2.5T Design, Dual-Side Active and Interconnects. - Haoran Lu; Yandong Ge; Xun Jiang 002; Jiacheng Sun; Wanyue Peng; Rui Guo; Ming Li; Yibo Lin; Runsheng Wang; Heng Wu 007; Ru Huang 001 (VLSI Technology and Circuits, 2024)

A Tale of Two Sides of Wafer: Physical Implementation and Block-Level PPA on Flip FET with Dual-Sided Signals. - Haoran Lu; Xun Jiang 002; Yanbang Chu; Ziqiao Xu; Rui Guo; Wanyue Peng; Yibo Lin; Runsheng Wang; Heng Wu 007; Ru Huang 001 (DATE, 2025)

A Systematic Approach for Multi-objective Double-side Clock Tree Synthesis. - Xun Jiang 002; Haoran Lu; Yuxuan Zhao 001; Jiarui Wang; Zizheng Guo; Heng Wu 007; Bei Yu 001; Sung Kyu Lim; Runsheng Wang; Ru Huang 001; Yibo Lin (CoRR, 2025)

A Robust FPGA Router With Optimization of High-Fanout Nets and Intra-CLB Connections. - Xun Jiang 002; Jiarui Wang; Jing Mai; Zhixiong Di; Yibo Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

PDNNet: PDN-Aware GNN-CNN Heterogeneous Network for Dynamic IR Drop Prediction. - Yuxiang Zhao; Zhuomin Chai; Xun Jiang 002; Yibo Lin; Runsheng Wang; Ru Huang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)