A 10Gbps CDR based on phase interpolator for source synchronous receiver in 65nm CMOS. - Shijie Hu; Chen Jia; Ke Huang 003; Chun Zhang; Xuqiang Zheng; Zhihua Wang 001 (ISCAS, 2012)

A 9.6Gb/s 5+1-lane source synchronous transmitter in 65nm CMOS technology. - Ke Huang 003; Chen Jia; Xuqiang Zheng; Ni Xu; Chun Zhang; Woogeun Rhee; Zhihua Wang 001 (ISCAS, 2012)

A current-to-voltage integrator using area-efficient correlated double sampling technique. - Xuqiang Zheng; Fule Li; Xuan Wang; Chun Zhang (ISCAS, 2012)

A novel clock and data recovery scheme for 10Gbps source synchronous receiver in 65nm CMOS. - Ke Huang 003; Ziqiang Wang; Xuqiang Zheng; Xuan Ma; Kunzhi Yu; Chun Zhang; Zhihua Wang 001 (MWSCAS, 2012)

A 6.4 Gb/s data lane design for forwarded clock receiver in 65nm CMOS. - Kunzhi Yu; Ziqiang Wang; Xuan Ma; Xuqiang Zheng; Chun Zhang; Zhihua Wang 001 (MWSCAS, 2012)

A 10Gb/s analog equalizer in 0.18um CMOS. - Linghan Wu; Ziqiang Wang; Ke Huang 003; Shuai Yuan 005; Xuqiang Zheng; Chun Zhang; Zhihua Wang 001 (ASICON, 2013)

A 10-Gb/s simplified transceiver with a quarter-rate 4-tap decision feedback equalizer in 0.18-μm CMOS technology. - Shuai Yuan 005; Ziqiang Wang; Xuqiang Zheng; Ke Huang 003; Liji Wu; Zhihua Wang 001 (ASICON, 2013)

A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS. - Kunzhi Yu; Xuqiang Zheng; Ke Huang 003; Xuan Ma; Ziqiang Wang; Chun Zhang; Zhihua Wang 001 (VLSI-DAT, 2013)

A 75mW 50Gbps SerDes transmitter with automatic serializing time window search in 65nm CMOS technology. - Ke Huang 003; Ziqiang Wang; Xuqiang Zheng; Chun Zhang; Zhihua Wang 001 (CICC, 2014)

A 4.8-mW/Gb/s 9.6-Gb/s 5 + 1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS. - Shuai Yuan 005; Ziqiang Wang; Xuqiang Zheng; Ke Huang 003; Ni Xu; Woogeun Rhee; Liji Wu; Chun Zhang (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A 50Gb/s low power PAM4 SerDes transmitter with 4-tap FFE and high linearity output voltage in 65nm CMOS technology. - Fangxu Lv; Xuqiang Zheng; Ziqiang Wang; Jianye Wang; Fule Li (ASICON, 2015)

A 190mW 40Gbps SerDes transmitter and receiver chipset in 65nm CMOS technology. - Ke Huang 003; Deng Luo; Ziqiang Wang; Xuqiang Zheng; Fule Li; Chun Zhang; Zhihua Wang 001 (CICC, 2015)

A 4×20-Gb/s 0.86pJ/b/lane 2-tap-FFE source-series-terminated transmitter with far-end crosstalk cancellation and divider-less clock generation in 65nm CMOS. - Shuai Yuan 005; Liji Wu; Ziqiang Wang; Xuqiang Zheng; Wen Jia; Chun Zhang; Zhihua Wang 001 (CICC, 2015)

A 48mW 15-to-28Gb/s source-synchronous receiver with adaptive DFE using hybrid alternate clock scheme and baud-rate CDR in 65nm CMOS. - Shuai Yuan 005; Liji Wu; Ziqiang Wang; Xuqiang Zheng; Peng Wang; Wen Jia; Chun Zhang; Zhihua Wang 001 (ESSCIRC, 2015)

A 40Gb/s 39mW 3-tap adaptive closed-loop decision feedback equalizer in 65nm CMOS. - Weidong Cao 001; Ziqiang Wang; Dongmei Li; Xuqiang Zheng; Fule Li; Chun Zhang; Zhihua Wang 001 (MWSCAS, 2015)

A 40Gb/s 27mW 3-tap closed-loop decision feedback equalizer in 65nm CMOS. - Weidong Cao 001; Ziqiang Wang; Dongmei Li; Xuqiang Zheng; Ke Huang 003; Shuai Yuan 005; Fule Li; Zhihua Wang 001 (NEWCAS, 2015)

A 80 mW 40 Gb/s Transmitter With Automatic Serializing Time Window Search and 2-tap Pre-Emphasis in 65 nm CMOS Technology. - Ke Huang 003; Ziqiang Wang; Xuqiang Zheng; Chun Zhang; Zhihua Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

An improved 40 Gb/s CDR with jitter-suppression filters and phase-compensating interpolators. - Xuqiang Zheng; Chun Zhang; Shuai Yuan 005; Feng Zhao 004; Shigang Yue; Ziqiang Wang; Fule Li; Zhihua Wang 001 (A-SSCC, 2016)

A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS. - Xuqiang Zheng; Chun Zhang; Fangxu Lv; Feng Zhao 004; Shigang Yue; Ziqiang Wang; Fule Li; Zhihua Wang 001 (ESSCIRC, 2016)

A 28-Gb/s transmitter with 3-tap FFE and T-coil enhanced terminal in 65-nm CMOS technology. - Naiwen Zhou; Linghan Wu; Ziqiang Wang; Xuqiang Zheng; Weidong Cao 001; Chun Zhang; Fule Li; Zhihua Wang 001 (NEWCAS, 2016)

A 70 mW 25 Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset With 40 dB of Equalization in 65 nm CMOS Technology. - Shuai Yuan 005; Liji Wu; Ziqiang Wang; Xuqiang Zheng; Chun Zhang; Zhihua Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process. - Xuqiang Zheng; Zhijun Wang; Fule Li; Feng Zhao 004; Shigang Yue; Chun Zhang; Zhihua Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

A 10 GHz 56 fsrms-integrated-jitter and -247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS. - Xuqiang Zheng; Fangxu Lv; Feng Zhao 004; Shigang Yue; Chun Zhang; Ziqiang Wang; Fule Li; Hanjun Jiang; Zhihua Wang 001 (CICC, 2017)

A 4-40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS. - Xuqiang Zheng; Chun Zhang; Fangxu Lv; Feng Zhao 004; Shigang Yue; Ziqiang Wang; Fule Li; Hanjun Jiang; Zhihua Wang 001 (CICC, 2017)

A battery-less, 255 nA quiescent current temperature sensor with voltage regulator fully powered by harvesting ambient vibrational energy. - Shiquan Fan; Liuming Zhao; Peng Wang; Ran Wei; Xuqiang Zheng; Zenghui Wang 004; Philip X.-L. Feng (ISCAS, 2017)

A 40-80 Gb/s PAM4 wireline transmitter in 65nm CMOS technology. - Fangxu Lv; Xuqiang Zheng; Shuai Yuan 005; Ziqiang Wang; Yajun He; Chun Zhang; Zhihua Wang 001; Jianye Wang (MWSCAS, 2017)

A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS. - Xuqiang Zheng; Chun Zhang; Fangxu Lv; Feng Zhao 004; Shuai Yuan 005; Shigang Yue; Ziqiang Wang; Fule Li; Zhihua Wang 001; Hanjun Jiang (IEEE J. Solid State Circuits, 2017)

A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications. - Fangxu Lv; Xuqiang Zheng; Feng Zhao 004; Jianye Wang; Shigang Yue; Ziqiang Wang; Weidong Cao 001; Yajun He; Chun Zhang; Hanjun Jiang; Zhihua Wang 001 (Microelectron. J., 2018)

Design of high-speed SerDes transceiver for chip-to-chip communications in CMOS process. - Xuqiang Zheng (2018)

A 112-Gb/s PAM-4 Transmitter With a 2-Tap Fractional-Spaced FFE in 65-nm CMOS. - Hao Ding; Xuqiang Zheng; DanYu Wu; Lei Zhou 014; Jin Wu; Fangxu Lv; Jianye Wang; Xinyu Liu 004 (ESSCIRC, 2019)

A 10-GS/s 8-bit 4-way interleaved folding ADC in 0.18 µm SiGe-BiCMOS. - Huasen Liu; DanYu Wu; Lei Zhou 014; Yinkun Huang; Jian Luan 002; Xuan Guo; Dong Wang 033; Xuqiang Zheng; Jin Wu; Xinyu Liu 004 (IEICE Electron. Express, 2019)

A CRNN System for Sound Event Detection Based on Gastrointestinal Sound Dataset Collected by Wearable Auscultation Devices. - Xuqiang Zheng; Chun Zhang; Ping Chen; Kang Zhao; Hanjun Jiang; Zhiwei Jiang; Huafeng Pan; Zhihua Wang 001; Wen Jia (IEEE Access, 2020)

A 50-112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS. - Xuqiang Zheng; Hao Ding; Feng Zhao 004; DanYu Wu; Lei Zhou 014; Jin Wu; Fangxu Lv; Jianye Wang; Xinyu Liu 004 (IEEE J. Solid State Circuits, 2020)

Frequency-Domain Modeling and Analysis of Injection-Locked Oscillators. - Xuqiang Zheng; Fangxu Lv; Lei Zhou 014; DanYu Wu; Jin Wu; Chun Zhang; Woogeun Rhee; Xinyu Liu 004 (IEEE J. Solid State Circuits, 2020)

A Robust Visual System for Small Target Motion Detection Against Cluttered Moving Backgrounds. - Hongxin Wang; Jigen Peng; Xuqiang Zheng; Shigang Yue (IEEE Trans. Neural Networks Learn. Syst., 2020)

A Real-Time Output 50-GS/s 8-bit TI-ADC with Dedicated Calibration Techniques and Deterministic Latency. - Jian Luan 002; Danyu Wu; Xuqiang Zheng; Chen Cai; Linzhen Wu; Lei Zhou 014; Jin Wu; Xinyu Liu 004 (ESSCIRC, 2021)

A 1.4-Vppd 64-Gb/s PAM-4 Transmitter with 4-Tap Hybrid FFE Employing Fractionally-Spaced Pre-Emphasis and Baud-Spaced De-Emphasis in 28-nm CMOS. - Chen Cai; Xuqiang Zheng; Yong Chen 005; Danyu Wu; Jian Luan 002; Lei Zhou 014; Jin Wu; Xinyu Liu 004 (ESSCIRC, 2021)

A CNRZ-7 Based Wireline Transceiver With High-Bandwidth-Density, Low-Power for D2D Communication. - Geng Zhang 001; Mingche Lai; Fangxu Lyu; Xuqiang Zheng; Heming Wang; Dongbin Lv; Chaolong Xu; Xingyun Qi; Qing Liu (IEEE Access, 2022)

A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS. - Mingche Lai; Geng Zhang 001; Fangxu Lv; Xuqiang Zheng; Heming Wang; Dongbin Lv; Chaolong Xu; Xingyun Qi (Microelectron. J., 2022)

A 50 Gb/s PAM-4 EAM driver in 28-nm CMOS technology. - Qiuyue Zhang; Xuqiang Zheng; Fangxu Lv; Zhaoyang Liu; Hua Xu; Weijie Li; Zhi Jin; Mingche Lai; Xinyu Liu (Microelectron. J., 2023)

A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter, and -76.5-dBc Reference Spur. - Tianle Chen; Hongyu Ren; Zunsong Yang; Yunbo Huang; Xianghe Meng; Weiwei Yan; Weidong Zhang; Xuqiang Zheng; Xuan Guo; Tetsuya Iizuka; Pui-In Mak; Yong Chen 005; et al. (VLSI Technology and Circuits, 2024)

A 200-Gb/s 70-GHz-bandwidth 2:1 analog multiplexer in 130-nm SiGe BiCMOS process. - Sijie Fan; Zedong Wang; Hua Xu; Hengyu Xu; Wenxiang Zhen; Xuqiang Zheng (IEICE Electron. Express, 2024)

A high-output-swing 64-Gb/s PAM-4 transmitter with a 4-tap hybrid FFE in 28-nm CMOS. - Hua Xu; Xuqiang Zheng; Zedong Wang; Chen Cai; Wenxiang Zhen; Guojun Yuan; Qinfen Hao; Xuan Guo; Zhi Jin (IEICE Electron. Express, 2024)

A fully digital timing background calibration algorithm based on first-order auto-correlation for time-interleaved ADCs. - Meng Li; Fangxu Lv; Mingche Lai; Xuqiang Zheng; Heng Huang; Xingyun Qi; Geng Zhang 001 (Microelectron. J., 2024)

A 56-Gb/s,0.708 pJ/bit single-ended simultaneous bidirectional transceiver with hybrid errors cancellation techniques for die-to-die interface. - Bolin Ren; Fangxu Lv; Mingche Lai; Liquan Xiao; Geng Zhang 001; Xuqiang Zheng; Zhang Luo; Jiaqing Xu (Microelectron. J., 2024)

Frequency Domain Modeling and Performance Analysis of Injection-Locked LC Oscillator. - Kewei Xin; Mingche Lai; Fangxu Lv; Xuqiang Zheng; Kaile Guo; Zhengbin Pang; Chaolong Xu; Geng Zhang 001; Wenchen Wang; Meng Li (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 25 Gb/s 5.99 pJ/bit SerDes receiver with CTLE and quarter-rate adaptive loop-unrolling 5-tap DFE in 28-nm CMOS technology for wireline medium-reach interconnection. - Zhaoyang Liu; Bao Chen; Zhanhao Wen; Xuqiang Zheng; Zedong Wang; Jiang Xu; Wenxiang Zhen (IEICE Electron. Express, 2025)

A 100 Gb/s PAM4 receiver analog front-end with 33.1-dB boost in 28-nm CMOS process. - Qiuyue Zhang; Xuqiang Zheng; Fangxu Lv; Wenxiang Zhen; Mingche Lai; Zhi Jin; Xinyu Liu 004 (IEICE Electron. Express, 2025)

A dual-channel half-rate 32 Gb/s, 5.3 pJ/bit SerDes transceiver with 3-tap-FFE and CTLE in 28-nm CMOS for very short reach C2C and C2M interconnection. - Zhaoyang Liu; Zhanhao Wen; Bao Chen; Jiang Xu; Zedong Wang; Xuqiang Zheng (Microelectron. J., 2025)

Ensemble network using oblique coronal MRI for Alzheimer's disease diagnosis. - Cunhao Li; Zhongjian Gao; Xiaomei Chen; Xuqiang Zheng; Xiaoman Zhang; Chih-Yang Lin (NeuroImage, 2025)

A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Utilizing a Complementary-Injection Scheme and an Adaptive Pulsewidth Adjustment. - Zedong Wang; Xuqiang Zheng; Yu He; Hua Xu; Sai Li; Zunsong Yang; Fangxu Lv; Mingche Lai; Xinyu Liu 004 (IEEE J. Solid State Circuits, 2025)

A 112-Gb/s PAM-4 Retimer Transceiver With Jitter-Filtering Clocking Scheme and BER Optimization Technique in 28-nm CMOS. - Hua Xu; Mingche Lai; Xuqiang Zheng; Zedong Wang; Jiang Xu; Sai Li; Fangxu Lv; Min Liu; Weijie Li; Zhanhao Wen; Xuan Guo; Xinhua Wang; et al. (IEEE J. Solid State Circuits, 2025)