Process technology and design parameter impact on SRAM Bit-Cell Sleep effectiveness. - Gururaj Shamanna; Bhunesh S. Kshatri; Raja Gaurav; Y. S. Tew; Percy Marfatia; Y. K. Raghavendra; V. Naik (SoCC, 2010)

Using ECC and redundancy to minimize vmin induced yield loss in 6T SRAM arrays. - Gururaj Shamanna; Raja Gaurav; Y. K. Raghavendra; Percy Marfatia; Bhunesh S. Kshatri (ICICDT, 2012)