Characterization of Critical Peak Current and General Model of Interconnect Systems Under Short Pulse-Width Conditions. - Ming-Hsien Lin; W. S. Chou; Y. T. Yang; A. S. Oates (IRPS, 2019)

Resistive-Gate RAM: An 1TnR Architecture Feasible for Scaling Beyond 16nm CMOS Generation. - C. H. Sung; M. J. Huang; Y. J. Li; Y. T. Yang; Y. R. Liu; P. H. Shih; J. C. Guo; Steve S. Chung (IRPS, 2025)