Reliability Evaluation and Redesign of LNA. - Wei-Cheng Lin; Long-Jei Du; Ya-Chin King (Microelectron. Reliab., 2004)

Novel self-convergent scheme logic-process-based multilevel/analog EEPROM memory. - Kung-Hong Lee; Shih-Chen Wang; Ya-Chin King (MTDT, 2005)

A novel single poly-silicon EEPROM using trench floating gate. - Meng-Yi Wu; Shin-Chang Feng; Ya-Chin King (MTDT, 2005)

Gate stress effect on low temperature data retention characteristics of split-gate flash memories. - Ling-Chang Hu; An-Chi Kang; Eric Chen; J. R. Shih; Yao-Feng Lin; Kenneth Wu; Ya-Chin King (Microelectron. Reliab., 2005)

Low-cost logarithmic CMOS image sensing by nonlinear analog-to-digital conversion. - Ying-Chieh Chuang; Shih-Fang Chen; Shi-Yu Huang; Ya-Chin King (IEEE Trans. Consumer Electron., 2005)

An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory. - Meng-Fan Chang; Shin-Jang Shen; Chia-Chi Liu; Che-Wei Wu; Yu-Fan Lin; Shang-Chi Wu; Chia-En Huang; Han-Chao Lai; Ya-Chin King; Chorng-Jung Lin; Hung-Jen Liao; Yu-Der Chih; et al. (ISSCC, 2011)

A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time. - Meng-Fan Chang; Che-Wei Wu; Chia-Chen Kuo; Shin-Jang Shen; Ku-Feng Lin; Shu-Meng Yang; Ya-Chin King; Chorng-Jung Lin; Yu-Der Chih (ISSCC, 2012)

An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory. - Meng-Fan Chang; Shin-Jang Shen; Chia-Chi Liu; Che-Wei Wu; Yu-Fan Lin; Ya-Chin King; Chorng-Jung Lin; Hung-Jen Liao; Yu-Der Chih; Hiroyuki Yamauchi (IEEE J. Solid State Circuits, 2013)

A Low-Voltage Bulk-Drain-Driven Read Scheme for Sub-0.5 V 4 Mb 65 nm Logic-Process Compatible Embedded Resistive RAM (ReRAM) Macro. - Meng-Fan Chang; Che-Wei Wu; Chia-Chen Kuo; Shin-Jang Shen; Sue-Meng Yang; Ku-Feng Lin; Wen-Chao Shen; Ya-Chin King; Chorng-Jung Lin; Yu-Der Chih (IEEE J. Solid State Circuits, 2013)

A low-power subthreshold-to-superthreshold level-shifter for sub-0.5V embedded resistive RAM (ReRAM) macro in ultra low-voltage chips. - Meng-Fan Chang; Che-Wei Wu; Jui-Yu Hung; Ya-Chin King; Chomg-Jung Lin; Mon-Shu Ho; Chia-Cheng Kuo; Shyh-Shyuan Sheu (APCCAS, 2014)

19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme. - Meng-Fan Chang; Jui-Jen Wu; Tun-Fei Chien; Yen-Chen Liu; Ting-Chin Yang; Wen-Chao Shen; Ya-Chin King; Chorng-Jung Lin; Ku-Feng Lin; Yu-Der Chih; Sreedhar Natarajan; Tsung-Yung Jonathan Chang (ISSCC, 2014)

Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme. - Meng-Fan Chang; Chia-Chen Kuo; Shyh-Shyuan Sheu; Chorng-Jung Lin; Ya-Chin King; Frederick T. Chen; Tzu-Kun Ku; Ming-Jinn Tsai; Jui-Jen Wu; Yu-Der Chih (IEEE J. Solid State Circuits, 2014)

Challenges and Circuit Techniques for Energy-Efficient On-Chip Nonvolatile Memory Using Memristive Devices. - Meng-Fan Chang; Albert Lee; Pin-Cheng Chen; Chrong Jung Lin; Ya-Chin King; Shyh-Shyuan Sheu; Tzu-Kun Ku (IEEE J. Emerg. Sel. Topics Circuits Syst., 2015)

Low VDDmin Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations. - Meng-Fan Chang; Jui-Jen Wu; Tun-Fei Chien; Yen-Chen Liu; Ting-Chin Yang; Wen-Chao Shen; Ya-Chin King; Chrong Jung Lin; Ku-Feng Lin; Yu-Der Chih; Tsung-Yung Jonathan Chang (IEEE J. Solid State Circuits, 2015)

7.4 A 256b-wordlength ReRAM-based TCAM with 1ns search-time and 14× improvement in wordlength-energyefficiency-density product using 2.5T1R cell. - Chien-Chen Lin; Jui-Yu Hung; Wen-Zhang Lin; Chieh-Pu Lo; Yen-Ning Chiang; Hsiang-Jen Tsai; Geng-Hau Yang; Ya-Chin King; Chrong Jung Lin; Tien-Fu Chen; Meng-Fan Chang (ISSCC, 2016)

4.7 A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic. - Yongpan Liu; Zhibo Wang 004; Albert Lee; Fang Su; Chieh-Pu Lo; Zhe Yuan; Chien-Chen Lin; Qi Wei 001; Yu Wang 002; Ya-Chin King; Chrong Jung Lin; Pedram Khalili; et al. (ISSCC, 2016)

A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors. - Albert Lee; Chieh-Pu Lo; Chien-Chen Lin; Wei-Hao Chen; Kuo-Hsiang Hsu; Zhibo Wang 004; Fang Su; Zhe Yuan; Qi Wei 001; Ya-Chin King; Chrong Jung Lin; Hochul Lee; et al. (IEEE J. Solid State Circuits, 2017)

A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed. - Zhibo Wang 004; Yongpan Liu; Albert Lee; Fang Su; Chieh-Pu Lo; Zhe Yuan; Jinyang Li 002; Chien-Chen Lin; Wei-Hao Chen; Hsiao-Yun Chiu; Wei-En Lin; Ya-Chin King; et al. (IEEE J. Solid State Circuits, 2017)

A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors. - Wei-Hao Chen; Kai-Xiang Li; Wei-Yu Lin; Kuo-Hsiang Hsu; Pin-Yi Li; Cheng-Han Yang; Cheng-Xin Xue; En-Yu Yang; Yen-Kai Chen; Yun-Sheng Chang; Tzu-Hsiang Hsu; Ya-Chin King; et al. (ISSCC, 2018)

A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors. - Cheng-Xin Xue; Wei-Hao Chen; Je-Syu Liu; Jia-Fang Li; Wei-Yu Lin; Wei-En Lin; Jing-Hong Wang; Wei-Chen Wei; Ting-Wei Chang; Tung-Cheng Chang; Tsung-Yuan Huang; Hui-Yao Kao; et al. (ISSCC, 2019)

FinFET CMOS logic gates with non-volatile states for reconfigurable computing systems. - Yu-Fan Chiang; Wei-Yu Chien; Yue-Der Chih; Jonathan Chang; Chrong Jung Lin; Ya-Chin King (Integr., 2019)

A ReRAM Macro Using Dynamic Trip-Point-Mismatch Sampling Current-Mode Sense Amplifier and Low-DC Voltage-Mode Write-Termination Scheme Against Resistance and Write-Delay Variation. - Chieh-Pu Lo; Wen-Zhang Lin; Wei-Yu Lin; Huan-Ting Lin; Tzu-Hsien Yang; Yen-Ning Chiang; Ya-Chin King; Chrong Jung Lin; Yu-Der Chih; Tsung-Yung Jonathon Chang; Meng-Fan Chang (IEEE J. Solid State Circuits, 2019)

Self-Convergent Trimming SRAM True Random Number Generation With In-Cell Storage. - Po-Shao Yeh; Chih-An Yang; Yi-Hong Chang; Yue-Der Chih; Chrong Jung Lin; Ya-Chin King (IEEE J. Solid State Circuits, 2019)

Dynamic pH Sensor with Embedded Calibration Scheme by Advanced CMOS FinFET Technology. - Chien-Ping Wang; Ying-Chun Shen; Peng-Chun Liou; Yu-Lun Chueh; Yue-Der Chih; Jonathan Chang; Chrong Jung Lin; Ya-Chin King (Sensors, 2019)

Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors. - Cheng-Xin Xue; Ting-Wei Chang; Tung-Cheng Chang; Hui-Yao Kao; Yen-Cheng Chiu; Chun-Ying Lee; Ya-Chin King; Chrong Jung Lin; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Wei-Hao Chen; et al. (IEEE J. Solid State Circuits, 2020)

High Density Embedded 3D Stackable Via RRAM in Advanced MCU Applications. - Yao-Hung Huang; Yu-Cheng Hsieh; Yu-Cheng Lin; Yue-Der Chih; Eric Wang; Jonathan Chang; Ya-Chin King; Chrong Jung Lin (VLSI Technology and Circuits, 2023)