A multicycle communication architecture and synthesis flow for Global interconnect Resource Sharing. - Wei-Sheng Huang; Yu-Ru Hong; Juinn-Dar Huang; Ya-Shih Huang (ASP-DAC, 2008)

Simultaneous data transfer routing and scheduling for interconnect minimization in multicycle communication architecture. - Yu-Ju Hong; Ya-Shih Huang; Juinn-Dar Huang (ASP-DAC, 2009)

Communication Synthesis for Interconnect Minimization in Multicycle Communication Architecture. - Ya-Shih Huang; Yu-Ju Hong; Juinn-Dar Huang (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Layer-Aware Design Partitioning for Vertical Interconnect Minimization. - Ya-Shih Huang; Yang-Hsiang Liu; Juinn-Dar Huang (ISVLSI, 2011)

Thermal-aware logic block placement for 3D FPGAs considering lateral heat dissipation (abstract only). - Juinn-Dar Huang; Ya-Shih Huang; Mi-Yu Hsu; Han-Yuan Chang (FPGA, 2012)

TherWare: Thermal-Aware Placement and Routing Framework for 3D FPGAs with Location-Based Heat Balance. - Ya-Shih Huang; Han-Yuan Chang; Juinn-Dar Huang (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)