Logic design automation of diagnosable MOS combinational logic networks. - Yacoub M. El-Ziq; Stephen Y. H. Su (DAC, 1977)

Logic design automation of MOS combinational networks with fan-in, fan-out constraints. - Yacoub M. El-Ziq (DAC, 1978)

Computer-Aided Logic Design of Two-Level MOS Combinational Networks with Statistical Results. - Yacoub M. El-Ziq; Stephen Y. H. Su (IEEE Trans. Computers, 1978)

Testing of MOS combinational networks a procedure for efficient fault simulation and test generation. - Yacoub M. El-Ziq (DAC, 1979)

A new test pattern generation system. - Yacoub M. El-Ziq (DAC, 1980)

Automatic test generation for stuck-open faults in CMOS VLSI. - Yacoub M. El-Ziq (DAC, 1981)

Functional-Level Test Generation for Stuck-Open Faults in CMOS VLSI. - Yacoub M. El-Ziq; Richard J. Cloutier (ITC, 1981)

Fault Diagnosis of MOS Combinational Networks. - Yacoub M. El-Ziq; Stephen Y. H. Su (IEEE Trans. Computers, 1982)

A Mixed-Mode Built-In Self-Test Technique Using Scan Path and Signature Analysis. - Yacoub M. El-Ziq; Hamid H. Butt (ITC, 1983)

Impact of Mixed-Mode Self Test on Life Cycle Cost of VLSI Based Design. - Yacoub M. El-Ziq; Hamid H. Butt (ITC, 1984)

A Hardware Accelerator for Maze Routing. - Youngju Won; Sartaj Sahni; Yacoub M. El-Ziq (IEEE Trans. Computers, 1990)

An ATPG Driver Selection Algorithm for Interconnect Test with Boundary Scan. - Wei-Cheng Her; Lin-Ming Jin; Yacoub M. El-Ziq (ITC, 1992)