Design of a VME Parametrized Library for FPGAs. - José Luis Ruiz; Yago Torroja; José Luis García (FPL, 1996)

Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models. - Teresa Riesgo; Yago Torroja; Eduardo de la Torre; Javier Uceda (DATE, 1998)

Design methodologies based on hardware description languages. - Teresa Riesgo; Yago Torroja; Eduardo de la Torre (IEEE Trans. Ind. Electron., 1999)

Switching activity propagation of VHDL-RTL combinational designs through an automated tool. - Felipe Machado; Teresa Riesgo; Yago Torroja (ICECS, 2005)

A Method for Switching Activity Analysis of VHDL-RTL Combinatorial Circuits. - Felipe Machado; Teresa Riesgo; Yago Torroja (PATMOS, 2006)

Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level. - Felipe Machado; Teresa Riesgo; Yago Torroja (PATMOS, 2008)

A Binary Decision Diagram Structure for Probabilistic Switching Activity Estimation. - Felipe Machado; Yago Torroja; Teresa Riesgo (J. Low Power Electron., 2008)