An area efficient 64-bit square root carry-select adder for low power applications. - Yajuan He; Chip-Hong Chang; Jiangmin Gu (ISCAS (4), 2005)

A novel covalent redundant binary Booth encoder. - Yajuan He; Chip-Hong Chang; Jiangmin Gu; Hossam A. H. Fahmy (ISCAS (1), 2005)

A low-power, high-speed RB-to-NB converter for fast redundant binary multiplier. - Yajuan He; Chip-Hong Chang (ISCAS, 2006)

A Power-Delay Efficient Hybrid Carry-Lookahead/Carry-Select Based Redundant Binary to Two's Complement Converter. - Yajuan He; Chip-Hong Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

A New Redundant Binary Booth Encoding for Fast 2n-Bit Multiplier Design. - Yajuan He; Chip-Hong Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Blind-LMS based digital background calibration for a 14-Bit 200-MS/s pipelined ADC. - Yajuan He; Bo Chen; Qiang Li 021 (VLSI-SoC, 2013)

Digital Error Corrector for Phase Lead-Compensated Buck Converter in DVS Applications. - Shaowei Zhen; Xiaohui Zhu; Ping Luo 005; Yajuan He; Bo Zhang 027 (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Study on Survey Methods for Crop Area Change Reasons at National Scale. - Quan Wu; Hualang Hu; Yanxia Liu; Danqiong Wang; Xinyu Duan; Lijuan Jia; Yajuan He (CCTA, 2014)

A 14-bit 100MS/s pipelined A/D converter with 2b interstage redundancy. - Kun Ao; Yajuan He; Liang Li; Yuxin Wang; Qiang Li 021 (ISIC, 2014)

A digital calibration technique for multi-bit-per-stage pipelined ADC. - Yajuan He; Song Wang; Qi Ling; Qiang Li 021 (ISIC, 2014)

Simulation of Winter Wheat Yield with WOFOST in County Scale. - Shangjie Ma; Zhiyuan Pei; Yajuan He; Lianlin Wang; Zhiping Ma (CCTA (1), 2015)

The Methodology of Monitoring Crops with Remote Sensing at the National Scale. - Quan Wu; Li Sun; Yajuan He; Fei Wang; Danqiong Wang; Weijie Jiao; Haijun Wang; Xue Han (CCTA (1), 2015)

A fast and energy efficient binary-to-pseudo CSD converter. - Yajuan He; Ziji Zhang 001; Bin Ma 010; Jinpeng Li; Shaowei Zhen; Ping Luo 005; Qiang Li 021 (ISCAS, 2015)

A pulse skipping modulation with adaptive duty ratio in buck converter application. - Dongjun Wang; Ping Luo 005; Qing Hua; Shaowei Zhen; Yajuan He (IEICE Electron. Express, 2015)

Study on Simulation of Rice Yield with WOFOST in Heilongjiang Province. - Shangjie Ma; Zhiyuan Pei; Yajuan He (CCTA, 2016)

A digital-assistant time-to-amplitude converter with dynamic range improvement. - Zengxin Liu; Shaowei Zhen; Shuiqing Xi; Xinjiang Gao; Lei Yang; Jiongwei Zheng; He Tang; Yajuan He; Ping Luo 005; Bo Zhang 027 (ASICON, 2017)

A Probabilistic Prediction Based Fixed-Width Booth Multiplier. - Yajuan He; Xilin Yi; Bin Ma 010; Ziji Zhang 001; Bo Zhang 027 (APCCAS, 2018)

Digital PID Based on Pseudo Type-III Compensation for DC-DC Converter. - Jiajia Wang; Shaowei Zhen; Yajuan He; Penghao Zeng; Jiawei Chen; Wanli Zhou; Ping Luo 005; Bo Zhang 027 (APCCAS, 2018)

A Disturb-Free 10T SRAM Cell with High Read Stability and Write Ability for Ultra-Low Voltage Operations. - Jiubai Zhang; Yajuan He; Xiaoqing Wu; Bo Zhang 027 (APCCAS, 2018)

An Energy-Efficient Approximate DCT for Wireless Capsule Endoscopy Application. - Yan Xing; Ziji Zhang 001; Yiduan Qian; Qiang Li 021; Yajuan He (ISCAS, 2018)

Optimal Slope Ranking: An Approximate Computing Approach for Circuit Pruning. - Ziji Zhang 001; Yajuan He; Jin He; Xilin Yi; Qiang Li 021; Bo Zhang 027 (ISCAS, 2018)

A Low-Error Energy-Efficient Fixed-Width Booth Multiplier With Sign-Digit-Based Conditional Probability Estimation. - Ziji Zhang 001; Yajuan He (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Design of an Energy-Efficient Approximate Compressor for Error-Resilient Multiplications. - Xilin Yi; Haoran Pei; Ziji Zhang 001; Hang Zhou; Yajuan He (ISCAS, 2019)

A Subthreshold 10T SRAM Cell with Enhanced Read and Write Operations. - Jiubai Zhang; Xiaoqing Wu; Xilin Yi; Jiaxun Lv; Yajuan He (ISCAS, 2019)

A Half-Select Disturb-Free 11T SRAM Cell With Built-In Write/Read-Assist Scheme for Ultralow-Voltage Operations. - Yajuan He; Jiubai Zhang; Xiaoqing Wu; Xin Si; Shaowei Zhen; Bo Zhang 027 (IEEE Trans. Very Large Scale Integr. Syst., 2019)

15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips. - Xin Si; Yung-Ning Tu; Wei-Hsing Huang; Jian-Wei Su; Pei-Jung Lu; Jing-Hong Wang; Ta-Wei Liu; Ssu-Yen Wu; Ruhui Liu; Yen-Chi Chou; Zhixiao Zhang; Syuan-Hao Sie; et al. (ISSCC, 2020)

A Probabilistic Prediction-Based Fixed-Width Booth Multiplier for Approximate Computing. - Yajuan He; Xilin Yi; Ziji Zhang 001; Bin Ma 010; Qiang Li 021 (IEEE Trans. Circuits Syst., 2020)

A Time-Efficient Automatic Circuit Approximation Method. - Ziji Zhang 001; Yajuan He; Bo Zhang 031 (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Teaching Logic and Sequential Cell Characterization in Digital Integrated Circuits. - Yajuan He; Ziji Zhang 001; Xiong Zhou; Qiang Li 021 (ICETT, 2021)

Design of Approximate Multiplierless DCT with CSD Encoding for Image Processing. - Lulin Cai; Yiduan Qian; Yajuan He; Wen Feng (ISCAS, 2021)

A 40nm 1Mb 35.6 TOPS/W MLC NOR-Flash Based Computation-in-Memory Structure for Machine Learning. - Yuxin Zhang; Sitao Zeng; Zhiguo Zhu; Zhaolong Qin; Chen Wang 130; Jingjing Li 001; Sanfeng Zhang; Yajuan He; Chunmeng Dou; Xin Si; Meng-Fan Chang; Qiang Li 021 (ISCAS, 2021)

A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips. - Xin Si; Yung-Ning Tu; Wei-Hsing Huang; Jian-Wei Su; Pei-Jung Lu; Jing-Hong Wang; Ta-Wei Liu; Ssu-Yen Wu; Ruhui Liu; Yen-Chi Chou; Yen-Lin Chung; William Shih; et al. (IEEE J. Solid State Circuits, 2021)

Design of Ultra-Low Power Consumption Approximate 4-2 Compressors Based on the Compensation Characteristic. - Haoran Pei; Xilin Yi; Hang Zhou; Yajuan He (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Design of Approximate Radix-256 Booth Encoding for Error-Tolerant Computing. - Feiyu Zhu; Shaowei Zhen; Xilin Yi; Haoran Pei; Bowen Hou; Yajuan He (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Fast-Transient Right-Half-Plane Zero-Free Hybrid Buck-Boost Converter. - Hao Chen; Shenhao Jiang; Shaowei Zhen; Yajuan He; Hailiang Xiong; Xin Chen; Hongyang Wu; Liang Huang; Yongsheng Du; Bo Zhang 027 (ASICON, 2023)

An 8T SRAM Based Digital Compute-In-Memory Macro For Multiply-And-Accumulate Accelerating. - Zilin Wang; Hongyang Luo; ZeYang Peng; Xingchen Chao; Yajuan He (ISCAS, 2023)

131TOPS/W 8b ACIM Exploiting Weight-Embedded Auto-Accumulation and Supporting Symmetric Quantization Networks. - Wei He; Puvi Bai; Hongyang Luo; Zhenghao Jin; Han Wu; Junyi Zhang; Xingchen Chao; Haiqi Liu; Yajuan He; Qiang Li 021 (CICC, 2024)