Low-voltage high driving capability CMOS buffer used in MEMS interface circuits. - Yajun Ha; M. F. Li; Ai Qun Liu (ICECS, 1999)

Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects. - Yajun Ha; Serge Vernalde; Patrick Schaumont; Marc Engels; Hugo De Man (PDPTA, 2000)

A Hardware Virtual Machine for the Networked Reconfiguration. - Yajun Ha; Patrick Schaumont; Marc Engels; Serge Vernalde; Freddy Potargent; Luc Rijnders; Hugo De Man (IEEE International Workshop on Rapid System Prototyping, 2000)

Virtual Java/FPGA interface for networked reconfiguration. - Yajun Ha; Geert Vanmeerbeeck; Patrick Schaumont; Serge Vernalde; Marc Engels; Rudy Lauwereins; Hugo De Man (ASP-DAC, 2001)

A SW/HW Interface API for Java/FPGA Co-Designed Applets. - Yajun Ha; Patrick Schaumont; Serge Vernalde; Marc Engels; Rudy Lauwereins; Hugo De Man (FCCM, 2001)

Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware. - Yajun Ha; Bingfeng Mei; Patrick Schaumont; Serge Vernalde; Rudy Lauwereins; Hugo De Man (FPL, 2001)

Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications. - Yajun Ha; Radovan Hipik; Serge Vernalde; Diederik Verkest; Marc Engels; Rudy Lauwereins; Hugo De Man (FPL, 2002)

Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects. - Yajun Ha; Serge Vernalde; Patrick Schaumont; Marc Engels; Rudy Lauwereins; Hugo De Man (J. Supercomput., 2002)

Design of Networked Reconfigurable Encryption Engine. - Shakith Fernando; Yajun Ha (FCCM, 2005)

An Embedded System to Support Tele-Medical Activity. - Jia Hui Ng; Chaur Lih Tan; Yajun Ha (Int. J. Softw. Eng. Knowl. Eng., 2005)

Design of Seamless Protocol Switching Layer for Voice Over Internet Protocol (Voip) That Switches Between Bluetooth and Ieee 802.11. - Yung Han Tan; Arun Krishnan Thampi; Daley Joseph Sebastian; Yajun Ha (Int. J. Softw. Eng. Knowl. Eng., 2005)

An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model. - Yu Pu; Yajun Ha (ASP-DAC, 2006)

Global Analysis of Resource Arbitration for MPSoC. - Akash Kumar 001; Bart Mesman; Henk Corporaal; Jef L. van Meerbergen; Yajun Ha (DSD, 2006)

Resource Manager for Non-preemptive Heterogeneous Multiprocessor System-on-chip. - Akash Kumar 001; Bart Mesman; Bart D. Theelen; Henk Corporaal; Yajun Ha (ESTIMedia, 2006)

A Probabilistic Approach to Model Resource Contention for Performance Estimation of Multi-featured Media Devices. - Akash Kumar 001; Bart Mesman; Henk Corporaal; Bart D. Theelen; Yajun Ha (DAC, 2007)

Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA. - Akash Kumar 001; Shakith Fernando; Yajun Ha; Bart Mesman; Henk Corporaal (FPL, 2007)

Fast and Accurate Interval-Based Timing Estimator for Variability-Aware FPGA Physical Synthesis Tools. - Chee Sing Lee 002; Wei Ting Loke; Wenjuan Zhang; Yajun Ha (FPL, 2007)

Vt balancing and device sizing towards high yield of sub-threshold static logic gates. - Yu Pu; José de Jesus Pineda de Gyvez; Henk Corporaal; Yajun Ha (ISLPED, 2007)

Statistical noise margin estimation for sub-threshold combinational circuits. - Yu Pu; José de Jesus Pineda de Gyvez; Henk Corporaal; Yajun Ha (ASP-DAC, 2008)

Dynamic scheduling of imprecise-computation tasks in maximizing QoS under energy constraints for embedded systems. - Heng Yu 001; Bharadwaj Veeravalli; Yajun Ha (ASP-DAC, 2008)

An Area-Efficient Timing-Driven Routing Algorithm for Scalable FPGAs with Time-Multiplexed Interconnects. - Hanyu Liu; Xiaolei Chen; Yajun Ha (FCCM, 2008)

sFPGA - A scalable switch based FPGA architecture and design methodology. - Shakith Fernando; Xiaolei Chen; Yajun Ha (FPL, 2008)

An architecture and timing-driven routing algorithm for area-efficient FPGAs with time-multiplexed interconnects. - Hanyu Liu; Xiaolei Chen; Yajun Ha (FPL, 2008)

Design of a high speed pseudo-random bit sequence based time resolved single photon counter on FPGA. - Haiting Tian; Shakith Fernando; Hock Wei Soon; Yajun Ha; Nanguang Chen (FPL, 2008)

A low overhead fault tolerant FPGA with new connection box. - Fujie Wong; Yajun Ha (FPL, 2008)

Tighter WCET analysis of input dependent programs with classified-cache memory architecture. - Yanhui Li; Shakith Fernando; Heng Yu 001; Xiaolei Chen; Yajun Ha; Teng Tiow Tay (ICECS, 2008)

Analyzing composability of applications on MPSoC platforms. - Akash Kumar 001; Bart Mesman; Bart D. Theelen; Henk Corporaal; Yajun Ha (J. Syst. Archit., 2008)

Interference-Minimized Multipath Routing with Congestion Control in Wireless Sensor Network for High-Rate Streaming. - Jenn-Yue Teo; Yajun Ha; Chen-Khong Tham (IEEE Trans. Mob. Comput., 2008)

Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA. - Akash Kumar 001; Shakith Fernando; Yajun Ha; Bart Mesman; Henk Corporaal (ACM Trans. Design Autom. Electr. Syst., 2008)

An optimized design for serial-parallel finite field multiplication over GF(2m) based on all-one polynomials. - Pramod Kumar Meher; Yajun Ha; Chiou-Yng Lee (ASP-DAC, 2009)

A Multi-Application Mapping Framework for Network-on-Chip Based MPSoC: An FPGA Implementation Case Study. - Guolei Zhu; Heng Yu 001; Yajun Ha; Yingmin Wang (ERSA, 2009)

sFPGA2 - A scalable GALS FPGA architecture and design methodology. - Rizwan Syed; Xiaolei Chen; Yajun Ha; Bharadwaj Veeravalli (FPL, 2009)

An ultra-low-energy/frame multi-standard JPEG co-processor in 65nm CMOS with sub/near-threshold power supply. - Yu Pu; José de Jesus Pineda de Gyvez; Henk Corporaal; Yajun Ha (ISSCC, 2009)

B*-tree based variability-aware floorplanning. - Wenjuan Zhang; Shefali Srivastava; Yajun Ha (APCCAS, 2010)

Leakage-aware dynamic scheduling for real-time adaptive applications on multiprocessor systems. - Heng Yu 001; Bharadwaj Veeravalli; Yajun Ha (DAC, 2010)

The Optimization of Interconnection Networks in FPGAs. - Xiaolei Chen; Yajun Ha (Dynamically Reconfigurable Architectures, 2010)

Mapping real-life applications on run-time reconfigurable NoC-based MPSoC on FPGA. - Amit Kumar Singh 002; Akash Kumar 001; Thambipillai Srikanthan; Yajun Ha (FPT, 2010)

An area-efficient dynamically reconfigurable Spatial Division Multiplexing network-on-chip with static throughput guarantee. - Zhiyao Joseph Yang; Akash Kumar 001; Yajun Ha (FPT, 2010)

Communication-aware application mapping and scheduling for NoC-based MPSoCs. - Heng Yu 001; Yajun Ha; Bharadwaj Veeravalli (ISCAS, 2010)

Performance-cost analyses software for H.264 Forward/Inverse Integer Transform. - Trang T. T. Do 001; Thinh M. Le; Binh P. Nguyen; Yajun Ha (International Symposium on Rapid System Prototyping, 2010)

An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS With Sub/Near Threshold Supply Voltage. - Yu Pu; José de Jesus Pineda de Gyvez; Henk Corporaal; Yajun Ha (IEEE J. Solid State Circuits, 2010)

Ultra Storage-Efficient Time Digitizer for Pseudorandom Single Photon Counter Implemented on a Field-Programmable Gate Array. - Haiting Tian; Shakith Fernando; Hock Wei Soon; Zhang Qiang; Chunxi Zhang; Yajun Ha; Nanguang Chen (IEEE Trans. Biomed. Circuits Syst., 2010)

Iterative Probabilistic Performance Prediction for Multi-Application Multiprocessor Systems. - Akash Kumar 001; Bart Mesman; Henk Corporaal; Yajun Ha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

A Hilbert curve-based delay fault characterization method for FPGAs. - Wenjuan Zhang; Yajun Ha (ISCAS, 2011)

A Routing Architecture for FPGAs with Dual-VT Switch Box and Logic Clusters. - Wei Ting Loke; Yajun Ha (ARC, 2012)

Power-aware FPGA technology mapping for programmable-VT architectures (abstract only). - Wei Ting Loke; Yajun Ha (FPGA, 2012)

Parallel dataflow execution for sequential programs on reconfigurable hybrid MPSoCs. - Chao Wang 003; Xi Li 003; Xuehai Zhou; Yajun Ha (FPT, 2012)

A Power and Cluster-Aware Technology Mapping and Clustering Scheme for Dual-VT FPGAs. - Wei Ting Loke; Yajun Ha; Wenfeng Zhao (IPDPS Workshops, 2012)

A low overhead abstract architecture for FPGA resource management. - Rizwan Syed; Yajun Ha; Bharadwaj Veeravalli (SIGARCH Comput. Archit. News, 2012)

TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs. - Mohammad Shihabul Haque; Akash Kumar 001; Yajun Ha; Qiang Wu; Shaobo Luo (ASP-DAC, 2013)

Dynamic Scheduling of Imprecise-Computation Tasks on Real-Time Embedded Multiprocessors. - Heng Yu 001; Bharadwaj Veeravalli; Yajun Ha; Shaobo Luo (CSE, 2013)

High Speed Video Processing Using Fine-Grained Processing on FPGA Platform. - Zhi Ping Ang; Akash Kumar 001; Yajun Ha (FCCM, 2013)

A directional coarse-grained power gated FPGA switch box and power gating aware routing algorithm. - Chin Hau Hoo; Yajun Ha; Akash Kumar 001 (FPL, 2013)

Criticality-based routing for FPGAS with reverse body bias switch box architectures. - Wei Ting Loke; Wenfeng Zhao; Yajun Ha (FPL, 2013)

FPGA based Rekeying for cryptographic key management in Storage Area Network. - Yi Wang 016; Yajun Ha (FPL, 2013)

sAES: A high throughput and low latency secure cloud storage with pipelined DMA based PCIe interface. - Yongzhen Chen; Miguel Rodel Felipe; Yi Wang 016; Yajun Ha; Shu Qin Ren; Khin Mi Mi Aung (FPT, 2013)

The architecture and placement algorithm for a uni-directional routing based 3D FPGA. - Junsong Hou; Heng Yu 001; Yajun Ha; Xin Liu (FPT, 2013)

An area-efficient shuffling scheme for AES implementation on FPGA. - Yi Wang 016; Yajun Ha (ISCAS, 2013)

Robustness-driven energy-efficient ultra-low voltage standard cell design with intra-cell mixed-Vt methodology. - Wenfeng Zhao; Yajun Ha; Chin Hau Hoo; Anastacia B. Alvarez (ISLPED, 2013)

Improved chaff point generation for vault scheme in bio-cryptosystems. - Thi Hanh Nguyen; Yi Wang 016; Yajun Ha; Renfa Li (IET Biom., 2013)

Quality-Driven Dynamic Scheduling for Real-Time Adaptive Applications on Multiprocessor Systems. - Heng Yu 001; Yajun Ha; Bharadwaj Veeravalli (IEEE Trans. Computers, 2013)

FPGA-Based 40.9-Gbits/s Masked AES With Area Optimization for Storage Area Network. - Yi Wang 016; Yajun Ha (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A 0.4V 280-nW frequency reference-less nearly all-digital hybrid domain temperature sensor. - Wenfeng Zhao; Rui Pan; Yajun Ha; Zhi Yang (A-SSCC, 2014)

Thermal-aware frequency scaling for adaptive workloads on heterogeneous MPSoCs. - Heng Yu 001; Rizwan Syed; Yajun Ha (DATE, 2014)

FPGA-based high throughput XTS-AES encryption/decryption for storage area network. - Yi Wang 016; Akash Kumar 001; Yajun Ha (FPT, 2014)

A heterogeneous platform with GPU and FPGA for power efficient high performance computing. - Qiang Wu; Yajun Ha; Akash Kumar 001; Shaobo Luo; Ang Li 006; Shihab Mohamed (ISIC, 2014)

A Performance and Area Efficient ASIP for Higher-Order DPA-Resistant AES. - Yi Wang 016; Yajun Ha (IEEE J. Emerg. Sel. Topics Circuits Syst., 2014)

A Low Active Leakage and High Reliability Phase Change Memory (PCM) Based Non-Volatile FPGA Storage Element. - Kejie Huang; Yajun Ha; Rong Zhao; Akash Kumar 001; Yong Lian 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Challenges and future trends for embedded security in electric vehicular communications. - Yi Wang 016; Zhiqian Hong; Jun Li 005; Shaobo Luo; Yajun Ha (ASICON, 2015)

ParaLaR: A parallel FPGA router based on Lagrangian relaxation. - Chin Hau Hoo; Akash Kumar 001; Yajun Ha (FPL, 2015)

AES architectures for minimum-energy operation and silicon demonstration in 65nm with lowest energy per encryption. - Wenfeng Zhao; Yajun Ha; Massimo Alioto (ISCAS, 2015)

Performance and security-enhanced fuzzy vault scheme based on ridge features for distorted fingerprints. - Thi Hanh Nguyen; Yi Wang 016; Yajun Ha; Renfa Li (IET Biom., 2015)

Correlation ratio based volume image registration on GPUs. - Ang Li 006; Akash Kumar 001; Yajun Ha; Henk Corporaal (Microprocess. Microsystems, 2015)

Reconfiguring Three-Dimensional Processor Arrays for Fault-Tolerance: Hardness and Heuristic Algorithms. - Guiyuan Jiang; Jigang Wu; Yajun Ha; Yi Wang 016; Jizhou Sun (IEEE Trans. Computers, 2015)

A 65-nm 25.1-ns 30.7-fJ Robust Subthreshold Level Shifter With Wide Conversion Range. - Wenfeng Zhao; Anastacia B. Alvarez; Yajun Ha (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study. - Wenfeng Zhao; Yajun Ha; Massimo Alioto (IEEE Trans. Very Large Scale Integr. Syst., 2015)

ParaFRo: A hybrid parallel FPGA router using fine grained synchronization and partitioning. - Chin Hau Hoo; Yajun Ha; Akash Kumar 001 (FPL, 2016)

High throughput and resource efficient AES encryption/decryption for SANs. - Yi Wang 016; Yajun Ha (ISCAS, 2016)

Unified data authenticated encryption for vehicular communication. - Yi Wang 016; Jianfeng An; Yajun Ha (MWSCAS, 2016)

Parallel Discord Discovery. - Tian Huang; Yongxin Zhu 001; Yishu Mao; Xinyang Li; Mengyun Liu; Yafei Wu; Yajun Ha; Gillian Dobbie (PAKDD (2), 2016)

An Optimized Logarithmic Converter With Equal Distribution of Relative Errors. - Mengyao Zhu; Yajun Ha; Chengcun Gu; Liuchuang Gao (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Analysis and design of energy-efficient data-dependent SRAM. - Wenfeng Zhao; Ang Li 006; Yi Wang 016; Yajun Ha (ASICON, 2017)

Quality Optimization of Resilient Applications under Temperature Constraints. - Heng Yu 001; Yajun Ha; Jing Wang (Conf. Computing Frontiers, 2017)

An energy-efficient system on a programmable chip platform for cloud applications. - Xu Wang 010; Yongxin Zhu 001; Yajun Ha; Meikang Qiu; Tian Huang; Xueming Si; Jiangxing Wu (J. Syst. Archit., 2017)

An FPGA-Based Cloud System for Massive ECG Data Analysis. - Xu Wang 010; Yongxin Zhu 001; Yajun Ha; Meikang Qiu; Tian Huang (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A DFA-Resistant and Masked PRESENT with Area Optimization for RFID Applications. - Yi Wang 016; Yajun Ha (ACM Trans. Embed. Comput. Syst., 2017)

Analytical Two-Level Near Threshold Cache Exploration for Low Power Biomedical Applications. - Yun Liang 001; Shuo Wang 009; Tulika Mitra; Yajun Ha (ACA, 2018)

A Hardware Pipeline with High Energy and Resource Efficiency for FMM Acceleration. - Tian Huang; Yongxin Zhu 001; Yajun Ha; Xu Wang 010; Meikang Qiu (ACM Trans. Embed. Comput. Syst., 2018)

Area-Efficient Distributed Arithmetic Optimization via Heuristic Decomposition and In-Memroy Computing. - Jian Chen; Wenfeng Zhao; Yajun Ha (ASICON, 2019)

Energy Efficiency Optimization of FPGA-based CNN Accelerators with Full Data Reuse and VFS. - Weixiong Jiang; Heng Yu 001; Xinzhe Liu; Yajun Ha (ICECS, 2019)

Area Efficient Box Filter Acceleration by Parallelizing with Optimized Adder Tree. - Xinzhe Liu; Fupeng Chen; Yajun Ha (ISVLSI, 2019)

Enabling Fine-Grained Dynamic Voltage and Frequency Scaling in SDSoC. - Weixiong Jiang; Heng Yu 001; Yajun Ha (SoCC, 2019)

AxC-CS: Approximate Computing for Hardware Efficient Compressed Sensing Encoder Design. - Wenfeng Zhao; Biao Sun; Jian Chen; Yajun Ha (SoCC, 2019)

Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base. - Yuanyong Luo; Yuxuan Wang; Yajun Ha; Zhongfeng Wang 001; Siyuan Chen; Hongbing Pan (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Corrections to "Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base". - Yuanyong Luo; Yuxuan Wang; Yajun Ha; Zhongfeng Wang 001; Siyuan Chen; Hongbing Pan (IEEE Trans. Very Large Scale Integr. Syst., 2019)

DVFS-Based Scrubbing Scheduling for Reliability Maximization on Parallel Tasks in SRAM-based FPGAs. - Rui Li 095; Heng Yu 001; Weixiong Jiang; Yajun Ha (DAC, 2020)

An Accurate FPGA Online Delay Monitor Supporting All Timing Paths. - Weixiong Jiang; Rui Li 095; Heng Yu 001; Yajun Ha (ISCAS, 2020)

Energy-Efficient Arbitrary Precision Multi-Bit Multiplication with Bi-Serial In/Near Memory Computing. - Yuqi Wang 004; Jian Chen; Yu Pu; Yajun Ha (ISCAS, 2020)

Optimization of FPGA Routing Networks with Time-Multiplexed Interconnects. - Ruiqi Luo; Xiaolei Chen; Yajun Ha (LASCAS, 2020)

Vulnerability of Deep Learning Model based Anomaly Detection in Vehicle Network. - Yi Wang 016; Dan Wei Ming Chia; Yajun Ha (MWSCAS, 2020)

Guest Editorial Special Issue on the 2020 IEEE International Symposium on Circuits and Systems. - Yajun Ha; Edoardo Bonizzoni (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Guest Editorial Special Issue on the 2020 ISICAS: A CAS Journal Track Symposium. - Yajun Ha; Edoardo Bonizzoni (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Efficient FPGA Implementation of K-Nearest-Neighbor Search Algorithm for 3D LIDAR Localization and Mapping in Smart Vehicles. - Hao Sun 035; Xinzhe Liu; Qi Deng; Weixiong Jiang; Shaobo Luo; Yajun Ha (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A Universal Method of Linear Approximation With Controllable Error for the Efficient Implementation of Transcendental Functions. - Huaqing Sun; Yuanyong Luo; Yajun Ha; Yinghuan Shi; Yang Gao 001; Qinghong Shen; Hongbing Pan (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Quality Estimation and Optimization of Adaptive Stereo Matching Algorithms for Smart Vehicles. - Fupeng Chen; Heng Yu 001; Yajun Ha (ACM Trans. Embed. Comput. Syst., 2020)

PLAC: Piecewise Linear Approximation Computation for All Nonlinear Unary Functions. - Hongxi Dong; Manzhen Wang; Yuanyong Luo; Muhan Zheng; Mengyu An; Yajun Ha; Hongbing Pan (IEEE Trans. Very Large Scale Integr. Syst., 2020)

TAIT: One-Shot Full-Integer Lightweight DNN Quantization via Tunable Activation Imbalance Transfer. - Weixiong Jiang; Heng Yu 001; Xinzhe Liu; Hao Sun; Rui Li 095; Yajun Ha (DAC, 2021)

Bitwidth-Optimized Energy-Efficient FFT Design via Scaling Information Propagation. - Xinzhe Liu; Fupeng Chen; Raees Kizhakkumkara Muhamad; David Blinder; Dessislava Nikolova; Peter Schelkens; Francky Catthoor; Yajun Ha (DAC, 2021)

A Fault Resistant AES via Input-Output Differential Tables with DPA Awareness. - Yi Wang 016; Marc Stöttinger; Yajun Ha (ISCAS, 2021)

CLIF: Cross-Layer Information Fusion for Stereo Matching and its Hardware Implementation. - Fupeng Chen; Xinzhe Liu; Heng Yu 001; Yajun Ha (ISCAS, 2021)

Hierarchical topometric representation of 3D robotic maps. - Zhenpeng He; Hao Sun; Jiawei Hou; Yajun Ha; Sören Schwertfeger (Auton. Robots, 2021)

DVFS-Based Quality Maximization for Adaptive Applications With Diminishing Return. - Heng Yu 001; Yajun Ha; Bharadwaj Veeravalli; Fupeng Chen; Hesham El-Sayed (IEEE Trans. Computers, 2021)

Analysis and Optimization Strategies Toward Reliable and High-Speed 6T Compute SRAM. - Jian Chen; Wenfeng Zhao; Yuqi Wang 004; Yajun Ha (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Analysis and Design of Reconfigurable Sense Amplifier for Compute SRAM With High-Speed Compute and Normal Read Access. - Jian Chen; Wenfeng Zhao; Yuqi Wang 004; Yajun Ha (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

An Optimized FPGA-Based Real-Time NDT for 3D-LiDAR Localization in Smart Vehicles. - Qi Deng; Hao Sun 035; Fupeng Chen; Yuhao Shu; Hui Wang 036; Yajun Ha (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Guest Editorial Special Issue on the 2021 IEEE International Symposium on Circuits and Systems. - Yajun Ha; Edoardo Bonizzoni (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Guest Editorial Special Issue on the 2021 ISICAS: A CAS Journal Track Symposium. - Yajun Ha; Edoardo Bonizzoni (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 55nm, 0.4V 5526-TOPS/W Compute-in-Memory Binarized CNN Accelerator for AIoT Applications. - Hongtu Zhang; Yuhao Shu; Weixiong Jiang; Zihan Yin; Wenfeng Zhao; Yajun Ha (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Hierarchical and Recursive Floorplanning Algorithm for NoC-Bascd Scalable Multi-Die FPGAs. - Jianwen Luo 004; Xinzhe Liu; Fupeng Chen; Yajun Ha (APCCAS, 2022)

WSQ-AdderNet: Efficient Weight Standardization Based Quantized AdderNet FPGA Accelerator Design with High-Density INT8 DSP-LUT Co-Packing Optimization. - Yunxiang Zhang; Biao Sun; Weixiong Jiang; Yajun Ha; Miao Hu; Wenfeng Zhao (ICCAD, 2022)

Unified Lightweight Authenticated Encryption for Resource-Constrained Electronic Control Unit. - Chunxu Guo; Yi Wang 016; Fupeng Chen; Yajun Ha (ICECS 2022, 2022)

An Ultra Energy Efficient Streaming-based FPGA Accelerator for Lightweight Neural Network. - Shaoyi Chen; Zhiqi Zhou; Yajun Ha (ISCAS, 2022)

Quality Optimization of Adaptive Applications via Deep Reinforcement Learning in Energy Harvesting Edge Devices. - Fupeng Chen; Heng Yu 001; Weixiong Jiang; Yajun Ha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

FPGA Accelerator for Real-Time Non-Line-of-Sight Imaging. - Zhengpeng Liao; Deyang Jiang; Xiaochun Liu; Andreas Velten; Yajun Ha; Xin Lou (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Ultra-Fast FPGA Implementation of Graph Cut Algorithm With Ripple Push and Early Termination. - Guangyao Yan; Xinzhe Liu; Fupeng Chen; Hui Wang 036; Yajun Ha (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Incoming Editorial. - Yajun Ha (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations. - Jian Chen; Wenfeng Zhao; Yuqi Wang 004; Yuhao Shu; Weixiong Jiang; Yajun Ha (IEEE Trans. Very Large Scale Integr. Syst., 2022)

FODM: A Framework for Accurate Online Delay Measurement Supporting All Timing Paths in FPGA. - Weixiong Jiang; Heng Yu 001; Hongtu Zhang; Yuhao Shu; Rui Li 095; Jian Chen; Yajun Ha (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A 40nm 0.35V 25MHz Half-Select Disturb-Free Bitinterleaving 10T SRAM With Data-Aware Write-Path. - Yifei Li; Jian Chen; Yuqi Wang 004; Zihan Yin; Hongyu Chen; Yajun Ha (CICC, 2023)

CIMC: A 603TOPS/W In-Memory-Computing C3T Macro with Boolean/Convolutional Operation for Cryogenic Computing. - Yuhao Shu; Hongtu Zhang; Qi Deng; Hao Sun 035; Yajun Ha (CICC, 2023)

Fast FPGA Accelerator of Graph Cut Algorithm with Out-of-order Parallel Execution in Folding Grid Architecture. - Guangyao Yan; Xinzhe Liu; Hui Wang 036; Yajun Ha (DAC, 2023)

An Energy-efficient and Fast KNN Search Accelerator for Large Scale Point Cloud Map. - Yunhao Hu; Hao Sun; Chunxu Guo; Qi Deng; Yajun Ha (ICECS, 2023)

Data Partition Optimization for High Energy Efficiency by Decoupling Local Dependence in Holographic Video Decoder. - Xinzhe Liu; Jianwen Luo 004; David Blinder; Fupeng Chen; Heng Yu 001; Peter Schelkens; Francky Catthoor; Yajun Ha (ICECS, 2023)

NORB: A Stream-Based and Non-Blocking FPGA Accelerator for ORB Feature Extraction. - Qixing Zhang; Hao Sun; Qi Deng; Heng Yu 001; Yajun Ha (ICECS, 2023)

CSDB-eDRAM: A 16Kb Energy-Efficient 4T CSDB Gain Cell eDRAM with over 16.6s Retention Time and 49.23uW/Kb at 4.2K for Cryogenic Computing. - Yuhao Shu; Hongtu Zhang; Hao Sun 035; Qi Deng; Yajun Ha (ISCAS, 2023)

RPS-KNN: An Ultra-Fast FPGA Accelerator of Range-Projection-Structure K-Nearest-Neighbor Search for LiDAR Odometry in Smart Vehicles. - Jianzhong Xiao; Hao Sun 035; Qi Deng; Xinzhe Liu; Hongtu Zhang; Chengzhang He; Yuhao Shu; Yajun Ha (ISCAS, 2023)

Cryogenic quasi-static embedded DRAM for energy-efficient compute-in-memory applications. - Yuhao Shu; Hongtu Zhang; Hao Sun 035; Mengru Zhang; Wenfeng Zhao; Qi Deng; Zhidong Tang; Yumeng Yuan; Yongqi Hu; Yu Gu; Xufeng Kou; Yajun Ha (CoRR, 2023)

An Energy-Efficient Stream-Based FPGA Implementation of Feature Extraction Algorithm for LiDAR Point Clouds With Effective Local-Search. - Hao Sun 035; Qi Deng; Xinzhe Liu; Yuhao Shu; Yajun Ha (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A High-Throughput Full-Dataflow MobileNetv2 Accelerator on Edge FPGA. - Weixiong Jiang; Heng Yu 001; Yajun Ha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A Reliable and High-Speed 6T Compute-SRAM Design With Dual-Split-VDD Assist and Bitline Leakage Compensation. - Yuqi Wang 004; Shen Zhang; Yifei Li; Jian Chen; Wenfeng Zhao; Yajun Ha (IEEE Trans. Very Large Scale Integr. Syst., 2023)

AOS: An Automated Overclocking System for High-Performance CNN Accelerator Through Timing Delay Measurement on FPGA. - Weixiong Jiang; Heng Yu 001; Fupeng Chen; Yajun Ha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

WDVR-RAM: A 0.25-1.2 V, 2.6-76 POPS/W Charge-Domain In-Memory-Computing Binarized CNN Accelerator for Dynamic AIoT Workloads. - Hongtu Zhang; Yuhao Shu; Qi Deng; Hao Sun 035; Wenfeng Zhao; Yajun Ha (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A Recursion and Lock Free GPU-Based Logic Rewriting Framework Exploiting Both Intranode and Internode Parallelism. - Lin Li 079; Rui Li 095; Yajun Ha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Criticality-Aware Negotiation-Driven Scrubbing Scheduling for Reliability Maximization in SRAM-Based FPGAs. - Rui Li 095; Heng Yu 001; Lin Li 079; Yajun Ha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

HRFF: Hierarchical and Recursive Floorplanning Framework for NoC-Based Scalable Multidie FPGAs. - Jianwen Luo 004; Xinzhe Liu; Fupeng Chen; Yajun Ha (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Outgoing Editorial. - Yajun Ha (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

The Optimization of Aging-aware 8T SRAM for FPGA Configuration Memory. - Yifei Li; Yuxin Zhou; Yuhao Shu; Hongyu Chen; Yajun Ha (ISCAS, 2024)

EarFDA: A Lightweight and Energy-Efficient Fall Detection Accelerator for Ear-Worn Devices. - Zhaodong Lv; Hao Sun 035; Yuhao Shu; Yajun Ha (ISCAS, 2024)

Machine Learning with Real-time and Small Footprint Anomaly Detection System for In-Vehicle Gateway. - Yi Wang; Yuanjin Zheng; Yajun Ha (ISCAS, 2024)

Modeling and Optimization of XOR Gate Based on Stochastic Thermodynamics. - Xiaoxuan Peng; Xiaohu Ge; Yajun Ha (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Fast Constraints Tuning via Transfer Learning and Multiobjective Optimization. - Meng Zhang 010; Zheng Zhang; Yifan Niu; Jiayi Li; Zewei Chen; Guoqing Li; Yajun Ha; Tinghuan Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

eCIMC: A603.1-TOPS/W eDRAM-Based Cryogenic In-Memory Computing Accelerator Supporting Boolean/Convolutional Operations. - Yuhao Shu; Hongtu Zhang; Qi Deng; Hao Sun 035; Zhaodong Lv; Yifei Li; Yajun Ha (IEEE J. Solid State Circuits, 2024)

ROFD: Event-based 5k-fps Real-Time Optical Flow Detector for Transient Radiant Expanding Flares. - Shen Zhang; Boyi Wei; Jing Jin; Yibo Zhang; Wenzhe Zheng; Yan Shen; Weixiong Jiang; Chenyang Shi; Yajun Ha (ISCAS, 2025)

FiDRL: Flexible Invocation-Based Deep Reinforcement Learning for DVFS Scheduling in Embedded Systems. - Jingjin Li; Weixiong Jiang; Yuting He 002; Qingyu Yang; Anqi Gao; Yajun Ha; Ender Özcan; Ruibin Bai; Tianxiang Cui; Heng Yu 001 (IEEE Trans. Computers, 2025)

A Deep Investigation on Stealthy DVFS Fault Injection Attacks at DNN Hardware Accelerators. - Junge Xu; Fan Zhang 010; Wenguang Jin; Kun Yang 012; Zeke Wang; Weixiong Jiang; Yajun Ha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

RefSCAT: Formal Verification of Logic-Optimized Multipliers via Automated Reference Multiplier Generation and SCA-SAT Synergy. - Rui Li 095; Lin Li 079; Heng Yu 001; Masahiro Fujita; Weixiong Jiang; Yajun Ha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

RSQC: Recursive Sparse QUBO Construction for Quantum Annealing Machines. - Jianwen Luo 004; Yuhao Shu; Yajun Ha (IEEE Trans. Computers, 2025)

Fast FPGA Accelerator of Graph Cut Algorithm With Threshold Global Relabel and Inertial Push. - Guangyao Yan; Xinzhe Liu; Hui Wang 036; Yajun Ha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

QuantTPM: Efficient Mixed-Precision Quantization Framework for Tractable Probabilistic Models. - Shen Zhang; Bin Ning; Guangyao Yan; Xinzhe Liu; Weixiong Jiang; Yajun Ha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

A 5T0C eDRAM-Based Content Addressable Memory for High-Density Searching and Logic-in-Memory. - Jincheng Wang; Yuhao Shu; Lintao Lan; Yifei Li; Bin Ning; Yuxin Zhou; Hongtu Zhang; Yajun Ha (IEEE Trans. Very Large Scale Integr. Syst., 2025)