Quantifying acceleration: Power/performance trade-offs of application kernels in hardware. - Brandon Reagen; Yakun Sophia Shao; Gu-Yeon Wei; David M. Brooks (ISLPED, 2013)

Energy characterization and instruction-level energy model of Intel's Xeon Phi processor. - Yakun Sophia Shao; David M. Brooks (ISLPED, 2013)

ISA-independent workload characterization and its implications for specialized architectures. - Yakun Sophia Shao; David M. Brooks (ISPASS, 2013)

MachSuite: Benchmarks for accelerator design and customized architectures. - Brandon Reagen; Robert Adolf; Yakun Sophia Shao; Gu-Yeon Wei; David M. Brooks (IISWC, 2014)

Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures. - Yakun Sophia Shao; Brandon Reagen; Gu-Yeon Wei; David M. Brooks (ISCA, 2014)

The Aladdin Approach to Accelerator Design and Modeling. - Yakun Sophia Shao; Brandon Reagen; Gu-Yeon Wei; David M. Brooks (IEEE Micro, 2015)

Research Infrastructures for Hardware Accelerators - Yakun Sophia Shao; David M. Brooks (Morgan & Claypool Publishers, 2015)

Co-designing accelerators and SoC interfaces using gem5-Aladdin. - Yakun Sophia Shao; Sam Likun Xi; Vijayalakshmi Srinivasan; Gu-Yeon Wei; David M. Brooks (MICRO, 2016)

Using dynamic dependence analysis to improve the quality of high-level synthesis designs. - Rafael Garibotti; Brandon Reagen; Yakun Sophia Shao; Gu-Yeon Wei; David M. Brooks (ISCAS, 2017)

Methods and infrastructure in the era of accelerator-centric architectures. - Brandon Reagen; Yakun Sophia Shao; Sam Likun Xi; Gu-Yeon Wei; David Brooks 001 (MWSCAS, 2017)

A modular digital VLSI flow for high-productivity SoC design. - Brucek Khailany; Evgeni Khmer; Rangharajan Venkatesan; Jason Clemons; Joel S. Emer; Matthew Fojtik; Alicia Klinefelter; Michael Pellauer; Nathaniel Ross Pinckney; Yakun Sophia Shao; Shreesha Srinath; Christopher Torng; et al. (DAC, 2018)

Hardware Acceleration. - Martha A. Kim; Yakun Sophia Shao (IEEE Micro, 2018)

Assisting High-Level Synthesis Improve SpMV Benchmark Through Dynamic Dependence Analysis. - Rafael Garibotti; Brandon Reagen; Yakun Sophia Shao; Gu-Yeon Wei; David M. Brooks (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration. - Michael Pellauer; Yakun Sophia Shao; Jason Clemons; Neal Clayton Crago; Kartik Hegde; Rangharajan Venkatesan; Stephen W. Keckler; Christopher W. Fletcher; Joel S. Emer (ASPLOS, 2019)

A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology. - Rangharajan Venkatesan; Yakun Sophia Shao; Brian Zimmer; Jason Clemons; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (Hot Chips Symposium, 2019)

MAGNet: A Modular Accelerator Generator for Neural Networks. - Rangharajan Venkatesan; Yakun Sophia Shao; Miaorong Wang; Jason Clemons; Steve Dai; Matthew Fojtik; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Yanqing Zhang 002; Brian Zimmer; et al. (ICCAD, 2019)

Timeloop: A Systematic Approach to DNN Accelerator Evaluation. - Angshuman Parashar; Priyanka Raina; Yakun Sophia Shao; Yu-Hsin Chen; Victor A. Ying; Anurag Mukkara; Rangharajan Venkatesan; Brucek Khailany; Stephen W. Keckler; Joel S. Emer (ISPASS, 2019)

Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture. - Yakun Sophia Shao; Jason Clemons; Rangharajan Venkatesan; Brian Zimmer; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (MICRO, 2019)

SNAP: A 1.67 - 21.55TOPS/W Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference in 16nm CMOS. - Jie-Fang Zhang; Ching-En Lee; Chester Liu; Yakun Sophia Shao; Stephen W. Keckler; Zhengya Zhang (VLSI Circuits, 2019)

A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm. - Brian Zimmer; Rangharajan Venkatesan; Yakun Sophia Shao; Jason Clemons; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (VLSI Circuits, 2019)

Gemmini: An Agile Systolic Array Generator Enabling Systematic Evaluations of Deep-Learning Architectures. - Hasan Genc; Ameer Haj-Ali; Vighnesh Iyer; Alon Amid; Howard Mao; John Charles Wright; Colin Schmidt 001; Jerry Zhao; Albert J. Ou; Max Banister; Yakun Sophia Shao; Borivoje Nikolic; et al. (CoRR, 2019)

NeuroVectorizer: end-to-end vectorization with deep reinforcement learning. - Ameer Haj-Ali; Nesreen K. Ahmed; Theodore L. Willke; Yakun Sophia Shao; Krste Asanovic; Ion Stoica (CGO, 2020)

Invited: Chipyard - An Integrated SoC Research and Implementation Environment. - Alon Amid; David Biancolin; Abraham Gonzalez; Daniel Grubb; Sagar Karandikar; Harrison Liew; Albert Magyar; Howard Mao; Albert J. Ou; Nathan Pemberton; Paul Rigge; Colin Schmidt 001; et al. (DAC, 2020)

A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm. - Brian Zimmer; Rangharajan Venkatesan; Yakun Sophia Shao; Jason Clemons; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (IEEE J. Solid State Circuits, 2020)

Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs. - Alon Amid; David Biancolin; Abraham Gonzalez; Daniel Grubb; Sagar Karandikar; Harrison Liew; Albert Magyar; Howard Mao; Albert J. Ou; Nathan Pemberton; Paul Rigge; Colin Schmidt 001; et al. (IEEE Micro, 2020)

Commercial Products. - David A. Patterson 001; Yakun Sophia Shao (IEEE Micro, 2020)

Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration. - Hasan Genc; Seah Kim; Alon Amid; Ameer Haj-Ali; Vighnesh Iyer; Pranav Prakash; Jerry Zhao; Daniel Grubb; Harrison Liew; Howard Mao; Albert J. Ou; Colin Schmidt 001; et al. (DAC, 2021)

A 16mm2 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET. - Abraham Gonzalez; Jerry Zhao; Ben Korpan; Hasan Genc; Colin Schmidt 001; John Charles Wright; Ayan Biswas; Alon Amid; Farhana Sheikh; Anton Sorokin; Sirisha Kale; Mani Yalamanchi; et al. (ESSCIRC, 2021)

CoSA: Scheduling by Constrained Optimization for Spatial Accelerators. - Qijing Huang 001; Aravind Kalaiah; Minwoo Kang; James Demmel; Grace Dinh; John Wawrzynek; Thomas Norell; Yakun Sophia Shao (ISCA, 2021)

Vertically Integrated Computing Labs Using Open-Source Hardware Generators and Cloud-Hosted FPGAs. - Alon Amid; Albert J. Ou; Krste Asanovic; Yakun Sophia Shao; Borivoje Nikolic (ISCAS, 2021)

Memory-Efficient Hardware Performance Counters with Approximate-Counting Algorithms. - Jingyi Xu; Sehoon Kim 001; Borivoje Nikolic; Yakun Sophia Shao (ISPASS, 2021)

Simba: scaling deep-learning inference with chiplet-based architecture. - Yakun Sophia Shao; Jason Clemons; Rangharajan Venkatesan; Brian Zimmer; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (Commun. ACM, 2021)

SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference. - Jie-Fang Zhang; Ching-En Lee; Chester Liu; Yakun Sophia Shao; Stephen W. Keckler; Zhengya Zhang (IEEE J. Solid State Circuits, 2021)

Learning A Continuous and Reconstructible Latent Space for Hardware Accelerator Design. - Qijing Huang 001; Charles Hong; John Wawrzynek; Mahesh Subedar; Yakun Sophia Shao (ISPASS, 2022)

Efficient emotion recognition using hyperdimensional computing with combinatorial channel encoding and cellular automata. - Alisha Menon; Anirudh Natarajan; Reva Agashe; Daniel Sun 005; Melvin Aristio; Harrison Liew; Yakun Sophia Shao; Jan M. Rabaey (Brain Informatics, 2022)

MoCA: Memory-Centric, Adaptive Execution for Multi-Tenant Deep Neural Networks. - Seah Kim; Hasan Genc; Vadim Vadimovich Nikiforov; Krste Asanovic; Borivoje Nikolic; Yakun Sophia Shao (HPCA, 2023)

CDPU: Co-designing Compression and Decompression Processing Units for Hyperscale Systems. - Sagar Karandikar; Aniruddha N. Udipi; Junsun Choi; Joonho Whangbo; Jerry Zhao; Svilen Kanev; Edwin Lim; Jyrki Alakuijala; Vrishab Madduri; Yakun Sophia Shao; Borivoje Nikolic; Krste Asanovic; et al. (ISCA, 2023)

RoSÉ: A Hardware-Software Co-Simulation Infrastructure Enabling Pre-Silicon Full-Stack Robotics SoC Evaluation. - Dima Nikiforov; Shengjun Chris Dong; Chengyi Lux Zhang; Seah Kim; Borivoje Nikolic; Yakun Sophia Shao (ISCA, 2023)

DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators. - Charles Hong; Qijing Huang 001; Grace Dinh; Mahesh Subedar; Yakun Sophia Shao (MICRO, 2023)

AuRORA: Virtualized Accelerator Orchestration for Multi-Tenant Workloads. - Seah Kim; Jerry Zhao; Krste Asanovic; Borivoje Nikolic; Yakun Sophia Shao (MICRO, 2023)

Full Stack Optimization of Transformer Inference: a Survey. - Sehoon Kim 001; Coleman Hooper; Thanakul Wattanawong; Minwoo Kang; Ruohan Yan; Hasan Genc; Grace Dinh; Qijing Huang 001; Kurt Keutzer; Michael W. Mahoney; Yakun Sophia Shao; Amir Gholami (CoRR, 2023)

Code Transpilation for Hardware Accelerators. - Yuto Nishida; Sahil Bhatia; Shadaj Laddad; Hasan Genc; Yakun Sophia Shao; Alvin Cheung (CoRR, 2023)

SPEED: Speculative Pipelined Execution for Efficient Decoding. - Coleman Hooper; Sehoon Kim 001; Hiva Mohammadzadeh; Hasan Genc; Kurt Keutzer; Amir Gholami; Yakun Sophia Shao (CoRR, 2023)

Guest Editorial Introduction to the Special Issue on the 2022 IEEE International Solid-State Circuits Conference (ISSCC). - Masum Hossain; Arijit Raychowdhury; Sanu K. Mathew; Yakun Sophia Shao; Yih Wang (IEEE J. Solid State Circuits, 2023)

RoSÉ: A Hardware-Software Co-Simulation Infrastructure Enabling Pre-Silicon Full-Stack Robotics SoC Evaluation. - Dima Nikiforov; Shengjun Chris Dong; Chengyi Lux Zhang; Seah Kim; Borivoje Nikolic; Yakun Sophia Shao (Zenodo, 2023)

Next-Generation Domain-Specific Accelerators: From Hardware to System. - Yakun Sophia Shao (CICC, 2024)

DiffuseLoco: Real-Time Legged Locomotion Control with Diffusion from Offline Datasets. - Xiaoyu Huang; Yufeng Chi; Ruofeng Wang; Zhongyu Li 003; Xue Bin Peng; Yakun Sophia Shao; Borivoje Nikolic; Koushil Sreenath (CoRL, 2024)

FireAxe: Partitioned FPGA-Accelerated Simulation of Large-Scale RTL Designs. - Joonho Whangbo; Edwin Lim; Chengyi Lux Zhang; Kevin Anderson; Abraham Gonzalez; Raghav Gupta; Nivedha Krishnakumar; Sagar Karandikar; Borivoje Nikolic; Yakun Sophia Shao; Krste Asanovic (ISCA, 2024)

Design Approach for Die-to-Die Interfaces to Enable Energy-Efficient Chiplet Systems. - Vikram Jain; Wei Tang 010; Zuoguo Wu; Viansa Schmulbach; Yakun Sophia Shao; Zhengya Zhang; Borivoje Nikolic (ISLPED, 2024)

Stellar: An Automated Design Framework for Dense and Sparse Spatial Accelerators. - Hasan Nazim Genc; Hansung Kim 004; Prashanth Ganesh; Yakun Sophia Shao (MICRO, 2024)

KVQuant: Towards 10 Million Context Length LLM Inference with KV Cache Quantization. - Coleman Hooper; Sehoon Kim 001; Hiva Mohammadzadeh; Michael W. Mahoney; Yakun Sophia Shao; Kurt Keutzer; Amir Gholami (NeurIPS, 2024)

LLM-Aided Compilation for Tensor Accelerators. - Charles Hong; Sahil Bhatia; Altan Haan; Shengjun Kris Dong; Dima Nikiforov; Alvin Cheung; Yakun Sophia Shao (CoRR, 2024)

AuRORA: A Full-Stack Solution for Scalable and Virtualized Accelerator Integration. - Seah Kim; Jerry Zhao; Krste Asanovic; Borivoje Nikolic; Yakun Sophia Shao (IEEE Micro, 2024)

SuperNoVA: Algorithm-Hardware Co-Design for Resource-Aware SLAM. - Seah Kim; Roger Hsiao; Borivoje Nikolic; James Demmel; Yakun Sophia Shao (ASPLOS (1), 2025)

Virgo: Cluster-level Matrix Unit Integration in GPUs for Scalability and Energy Efficiency. - Hansung Kim 004; Ruohan Richard Yan; Joshua You; Tieliang Vamber Yang; Yakun Sophia Shao (ASPLOS (2), 2025)

ETS: Efficient Tree Search for Inference-Time Scaling. - Coleman Hooper; Sehoon Kim 001; Suhong Moon; Kerem Dilmen; Monishwaran Maheswaran; Nicholas Lee; Michael W. Mahoney; Yakun Sophia Shao; Kurt Keutzer; Amir Gholami (CoRR, 2025)

FGMP: Fine-Grained Mixed-Precision Weight and Activation Quantization for Hardware-Accelerated LLM Inference. - Coleman Hooper; Charbel Sakr; Ben Keller; Rangharajan Venkatesan; Kurt Keutzer; Yakun Sophia Shao; Brucek Khailany (CoRR, 2025)

Demonstrating Berkeley Humanoid Lite: An Open-source, Accessible, and Customizable 3D-printed Humanoid Robot. - Yufeng Chi; Qiayuan Liao; Junfeng Long; Xiaoyu Huang; Yakun Sophia Shao; Borivoje Nikolic; Zhongyu Li 003; Koushil Sreenath (CoRR, 2025)

LangWBC: Language-directed Humanoid Whole-Body Control via End-to-end Learning. - Yiyang Shao; Xiaoyu Huang; Bike Zhang; Qiayuan Liao; Yuman Gao; Yufeng Chi; Zhongyu Li 003; Yakun Sophia Shao; Koushil Sreenath (CoRR, 2025)

Autocomp: LLM-Driven Code Optimization for Tensor Accelerators. - Charles Hong; Sahil Bhatia; Alvin Cheung; Yakun Sophia Shao (CoRR, 2025)

hdl2v: A Code Translation Dataset for Enhanced LLM Verilog Generation. - Charles Hong; Brendan Roberts; Huijae An; Alex Um; Advay Ratan; Yakun Sophia Shao (CoRR, 2025)

Multipole Attention for Efficient Long Context Reasoning. - Coleman Hooper; Sebastian Zhao; Luca Manolache; Sehoon Kim 001; Michael W. Mahoney; Yakun Sophia Shao; Kurt Keutzer; Amir Gholami (CoRR, 2025)