Hardware/software system co-verification of an active reconfigurable board with SystemC-VHDL. - Yan Basile-Bellavance; Etienne Lepercq; Yves Blaquière; Yvon Savaria (ICECS, 2008)

Design and validation of a novel reconfigurable and defect tolerant JTAG scan chain. - Yves Blaquière; Yan Basile-Bellavance; Safa Berrima; Yvon Savaria (ISCAS, 2014)