A high-speed CMOS incrementer/decrementer. - Chung-Hsun Huang; Jinn-Shyan Wang; Yan-Chao Huang (ISCAS (4), 2001)

Design of high-performance CMOS priority encoders and incrementer/decrementers using multilevel lookahead and multilevel folding techniques. - Chung-Hsun Huang; Jinn-Shyan Wang; Yan-Chao Huang (IEEE J. Solid State Circuits, 2002)