A Fully Synthesizable Injection Locked PLL with Dual-DCO Frequency Tracking in 55nm CMOS. - Xuanchi Yu; Yan Chen 050; Gaofena Jin; Fei Feng; Xun Luo; Xiang Gao 028 (ICTA, 2022)

A Dual-Path SPD/PFD PLL With PVT-Insensitive Loop Bandwidth. - Yan Chen 050; Gaofeng Jin; Haojie Xu; Yu Cui; Lei Zeng; Xiang Gao 028 (IEEE Solid State Circuits Lett., 2025)

A Low-Jitter Fractional-N LC-PLL With a 1/4 DTC-Range-Reduction Technique. - Gaofeng Jin; Fei Feng; Yan Chen 050; Hanli Liu; Xiang Gao 028 (IEEE Solid State Circuits Lett., 2025)