Exploring a Bayesian Optimization Framework Compatible with Digital Standard Flow for Soft-Error-Tolerant Circuit. - Yan Li 084; Xiaoyoung Zeng; Zhengqi Gao; Liyu Lin; Jun Tao 001; Jun Han 003; Xu Cheng 002; Mehdi B. Tahoori; Xiaoyang Zeng (DAC, 2020)

A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application. - Yan Li 084; Xu Cheng 002; Chiyu Tan; Jun Han 003; Yuanfu Zhao; Liang Wang 024; Tongde Li; Mehdi B. Tahoori; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

TRIGON: A Single-phase-clocking Low Power Hardened Flip-Flop with Tolerance to Double-Node-Upset for Harsh Environments Applications. - Yan Li 084; Jun Han 003; Xiaoyang Zeng; Mehdi B. Tahoori (DATE, 2021)

General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework. - Chiyu Tan; Yan Li 084; Xu Cheng 002; Jun Han 003; Xiaoyang Zeng (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

An Improved Multi-Objective Optimization Framework for Soft-Error Immune Circuits. - Shaohang Chu; Yan Li 084; Xu Cheng 002; Xiaoyang Zeng (APCCAS, 2022)

A Non-Redundant Latch With Key-Node-Upset Obstacle of Beneficial Efficiency for Harsh Environments Applications. - Yan Liu; Yan Li 084; Xu Cheng 002; Jun Han 003; Xiaoyang Zeng (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

DMBF: Design Metrics Balancing Framework for Soft-Error-Tolerant Digital Circuits Through Bayesian Optimization. - Yan Li 084; Chao Chen; Xu Cheng 002; Jun Han 003; Xiaoyang Zeng (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Novel partial punch-through-stopper scheme for substrate leakage optimization of nanosheet field-effect transistors. - Huaizhi Luo; Yongliang Li; Fei Zhao; Jiayi Zhang; Yan Li 084 (Microelectron. J., 2024)

Examining the role of tap cell in suppressing single event transient effect in 28-nm CMOS technology. - Chenyu Zhang; Yan Li 084; Wenfa Zhan; Wenping Geng; Ting Liang; Xiaoyang Zeng (Microelectron. J., 2024)